Posts by florentb

florentb

Yes, it is working first time on JLink 7.68.
It is the exact same board, with the same JTrace, and exactly the same connections (the only change is the JLink software).

Code

λ jlink                                                               
SEGGER J-Link Commander V7.68 (Compiled Jul 14 2022 16:56:10)         
DLL version V7.68, compiled Jul 14 2022 16:54:28                      
Connecting to J-Link via USB...O.K.                                   
Firmware: J-Trace PRO V2 Cortex-M compiled Jun  6 2023 10:51:16       
Hardware version: V2.00                                               
J-Link uptime (since boot): 0d 00h 27m 42s                            
S/N: 752001898                                                        
License(s): RDI, FlashBP, FlashDL, JFlash, GDB                        
USB speed mode: Super speed (5 GBit/s)                                
IP-Addr: DHCP (no addr. received yet)                                 
Emulator has RAWTRACE capability                                      
VTref=1.826V                                                          
Type "connect" to establish a target connection, '?' for help         
J-Link>connect                                                        
Please specify device / core. <Default>: EFR32BG22CXXXF352            
Type '?' for selection dialog                                         
Device>STM32H730IB                                                    
Please specify target interface:                                      
  J) JTAG (Default)                                                   
  S) SWD                                                              
  T) cJTAG                                                            
TIF>s                                                                 
Specify target interface speed [kHz]. <Default>: 4000 kHz             
Speed>                                                                
Device "STM32H730IB" selected.                                        
Connecting to target via SWD                                          
ConfigTargetSettings() start                                          
ConfigTargetSettings() end                                            
Found SW-DP with ID 0x6BA02477                                        
STM32 (connect): Can not attach to CPU. Trying connect under reset.   
Found SW-DP with ID 0x6BA02477                                        
Active write protected STM32 device detected.                         
This could cause problems during flash download.                      
Note: Unsecuring will trigger a mass erase of the internal flash.     
Executing default behavior previously saved in the registry.          
Device will be unsecured now.                                         
Found SW-DP with ID 0x6BA02477                                        
DPIDR: 0x6BA02477                                                     
CoreSight SoC-400 or earlier                                          
Scanning AP map to find all available APs                             
AP[3]: Stopped AP scan as end of AP map has been reached              
AP[0]: AHB-AP (IDR: 0x84770001)                                       
AP[1]: AHB-AP (IDR: 0x84770001)                                       
AP[2]: APB-AP (IDR: 0x54770002)                                       
Iterating through AP map to find AHB-AP to use                        
AP[0]: Core found                                                     
AP[0]: AHB-AP ROM base: 0xE00FE000                                    
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)              
Found Cortex-M7 r1p2, Little endian.                                  
FPUnit: 8 code (BP) slots and 0 literal slots                         
CoreSight components:                                                 
ROMTbl[0] @ E00FE000                                                  
[0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table                  
ROMTbl[1] @ E00FF000                                                  
[1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7                     
[1][1]: E0001000 CID B105E00D PID 000BB002 DWT                        
[1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7                     
[1][3]: E0000000 CID B105E00D PID 000BB001 ITM                        
[0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7                     
[0][2]: E0043000 CID B105900D PID 004BB906 CTI                        
Cache: Separate I- and D-cache.                                       
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way                     
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way                     
Cortex-M7 identified.                                                 
J-Link>

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However, I am using the JTrace Pro, which I suspect not many people are using, so it may be broken since quite a long time.

Thanks,
Florent

florentb

Hello,
with the most recent versions of JLink, the connection to the STM32H730 takes many tries.
Typically I can connect in the JLink command line, but it takes two tries (the first "connect" will not work, while the second "connect" will work).
If I re-launch JLink command line, the same behavior happens again (the first "connect" will never work).

It was working with older JLink versions, so there must be a regression here.

Code

> jlink
SEGGER J-Link Commander V7.92b (Compiled Aug 23 2023 4:01:42)
DLL version V7.92b, compiled Aug 23 2023 14:00:04


Connecting to J-Link via USB...O.K.
Firmware: J-Trace PRO V2 Cortex-M compiled Jun  6 2023 10:51:16
Hardware version: V2.00
J-Link uptime (since boot): 8d 18h 29m 12s
S/N: 752001898
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
USB speed mode: Super speed (5 GBit/s)
IP-Addr: DHCP (no addr. received yet)
Emulator has RAWTRACE capability
VTref=1.779V
Type "connect" to establish a target connection, '?' for help


J-Link>connect
Please specify device / core. <Default>: STM32H730IB
Type '?' for selection dialog
Device>
Please specify target interface:
  J) JTAG (Default)
  S) SWD
  T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "STM32H730IB" selected.


Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 12us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.


SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 662ms
Connect failed. Resetting via Reset pin and trying again.


ConfigTargetSettings() start
ConfigTargetSettings() end - Took 8us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 661ms
Cannot connect to target.




J-Link>connect
Device "STM32H730IB" selected.
Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 7us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.


SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.


InitTarget() end - Took 658ms
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 7us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
InitTarget() end - Took 6.47ms
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x84770001)
AP[1]: AHB-AP (IDR: 0x84770001)
AP[2]: APB-AP (IDR: 0x54770002)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FE000
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
Cache: L1 I/D-cache present
Found Cortex-M7 r1p2, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FE000
[0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[1][1]: E0001000 CID B105E00D PID 000BB002 DWT
[1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[1][3]: E0000000 CID B105E00D PID 000BB001 ITM
[0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[0][2]: E0043000 CID B105900D PID 004BB906 CTI
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M7 identified.

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Thanks,
Florent

florentb

Hello,
we are using a JTrace PRO + Ozone 3.28, with a custom STM32H730IB board.
We are using a the 4-pins trace interface, with a low CPU frequency so that the trace can be working without issues (TRACECLK is 30MHz or so).
We also use the provided .pex file (ST_STM32H743_Traceconfig.pex) and load it in the Ozone project.

The problem is that the trace is only working before hitting the first breakpoint. We have the following behavior:
- if "Reset & Run" mode is used, the trace not working (we have the orange LED on the JTrace but the instruction trace stays empty)
- if "'Reset & Break at symbol" (main()) is used, the trace is working only before the main() breakpoint is hit. Then, when we click Continue, the Instruction trace counter stays at the same value and we don't get any more trace after that.
However, in both cases, the Trace packets counter is increasing in the JTrace control panel, so the trace packets are actually sent by the target and received by the JTrace adapter, but somehow not parsed / read by Ozone.

It is not linked to a clock configuration issue on the MCU side - we ended up by removing all the clock configuration from our code and the behavior stays exactly the same.

We can share the .elf file and Ozone project but obviously not publicly.

Thanks,
Florent

florentb

Hi Niklas,
thanks, the issue seems to be fixed on 5.10p!

Florent

florentb

No, you don't need to export the code to another IDE to reproduce the problem. I used only JLink to flash the .hex files and the issue is reproduced.

I tried with BLE_Battery_Level example. Check the attachement. Note that if you don't switch the SWD interface into GPIO mode, the issue is not present.
I also attached the .hex file with SWD in GPIO mode, you can also generate it with the IDE (in CortexM0\ARM_GCC_493\Debug\BLE_Battery_Level.hex).

I use the Cypress BLE Pionneer Kit, and I use the black daughter board (PRoC / CYBL10563), but the bug has been reproduced with other boards / devices as well (CYBL10461).
In JLink Commander : device CYBL10XXX, then I manually select SWD interface at default speed.
You can erase / loadfile BLE_Battery_Level.hex, but once done, JLink is unable to re-connect :
- directly on the Pionneer Kit board, it displays "WARNING: RESET (pin 15) high but should be low" and then ultimately "Can not connect to target".
- using the daughter board directly connected to JLink with some wires, when trying "connect" it just displays "Can not connect to target". With an oscilloscope we can see that JLink switches RESET pin high / low / high / low serveral times but that doesn't help. I think you need to have the RESET pin being low for some time before the SWD interface is enabled (and obviously if at any time during connecting JLink switch the RESET to high, the SWD interface will be disabled immediately).
- typing r0 in JLink Commander does switch RESET to low, but as soon as we try "connect", JLink switches the RESET pin back to high , which disables the SWD interface and prevents JLink from connecting.

As JLink can't be used anymore, you need to use the Cypress SWD Programmed (integrated on the Cypress BLE Pionneer Kit main board) to flash the MCU again.

Florent

florentb

Hi Niklas,
this issue is not be related to a specific project.

Just open any sample PSoC BLE project from Cypress in PSoC Creator, make the change SWD > GPIO as stated in AN92584, and that should do it.
Once the PSoC is flashed, JLink won't be able to connect to it again.

Florent

florentb

Check for example AN92584 at http://www.cypress.com/documentation/…attery-life-ble
At page 7/8 : SWD Pin Configuration, they explain how to configure it.

They say that the SWD pins are in GPIO mode normally, but "will still be available for programming the device upon chip reset.".

Florent

florentb

PSoCs have a mode where the SWD interface is enabled only in RESET mode; in order to reduce the power consumption.
Cypress call this "SWD in GPIO mode", check in the PSoC Creator IDE under System tab.

However it seems that JLink does not support a connect-under-RESET for PSoC devices.
When in SWD-GPIO mode, JLink can't connect at all, actually it does not even detect the SWD interface.

Trying to change rsettype to 3 returns an UNKNOWN type, and does not solve the problem.

Also, programming the PSoC with Cypress SWD programmer works without problem.

Device used : CYBL10461-56LQXI (PRoC with BLE) / can be tested with Cypress dev boards as well.
JLink version : V510i

Thanks,
Florent

Posts by florentb

[SOLVED] JLink takes several tries to connect to STM32H730

[SOLVED] JLink takes several tries to connect to STM32H730

[ABANDONED] Ozone 3.28 + JTrace PRO, trace not working after hitting breakpoint

[SOLVED] SWD connect fails on PSoC in low-power mode

[SOLVED] SWD connect fails on PSoC in low-power mode

[SOLVED] SWD connect fails on PSoC in low-power mode

[SOLVED] SWD connect fails on PSoC in low-power mode

[SOLVED] SWD connect fails on PSoC in low-power mode