[SOLVED] JLink takes several tries to connect to STM32H730

florentb · August 28, 2023 at 6:41 PM

Hello,
with the most recent versions of JLink, the connection to the STM32H730 takes many tries.
Typically I can connect in the JLink command line, but it takes two tries (the first "connect" will not work, while the second "connect" will work).
If I re-launch JLink command line, the same behavior happens again (the first "connect" will never work).

It was working with older JLink versions, so there must be a regression here.

Code

> jlink
SEGGER J-Link Commander V7.92b (Compiled Aug 23 2023 4:01:42)
DLL version V7.92b, compiled Aug 23 2023 14:00:04


Connecting to J-Link via USB...O.K.
Firmware: J-Trace PRO V2 Cortex-M compiled Jun  6 2023 10:51:16
Hardware version: V2.00
J-Link uptime (since boot): 8d 18h 29m 12s
S/N: 752001898
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
USB speed mode: Super speed (5 GBit/s)
IP-Addr: DHCP (no addr. received yet)
Emulator has RAWTRACE capability
VTref=1.779V
Type "connect" to establish a target connection, '?' for help


J-Link>connect
Please specify device / core. <Default>: STM32H730IB
Type '?' for selection dialog
Device>
Please specify target interface:
  J) JTAG (Default)
  S) SWD
  T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "STM32H730IB" selected.


Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 12us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.


SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 662ms
Connect failed. Resetting via Reset pin and trying again.


ConfigTargetSettings() start
ConfigTargetSettings() end - Took 8us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 661ms
Cannot connect to target.




J-Link>connect
Device "STM32H730IB" selected.
Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 7us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.


SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Timeout while waiting for CPU to halt.
Connecting to CPU via connect under reset failed.


InitTarget() end - Took 658ms
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 7us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
InitTarget() end - Took 6.47ms
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x84770001)
AP[1]: AHB-AP (IDR: 0x84770001)
AP[2]: APB-AP (IDR: 0x54770002)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FE000
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
Cache: L1 I/D-cache present
Found Cortex-M7 r1p2, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FE000
[0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[1][1]: E0001000 CID B105E00D PID 000BB002 DWT
[1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[1][3]: E0000000 CID B105E00D PID 000BB001 ITM
[0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[0][2]: E0043000 CID B105900D PID 004BB906 CTI
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M7 identified.

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Thanks,
Florent

SEGGER - Alex · September 6, 2023 at 8:57 PM

Can you post a screenshot of the old version that shows that multiple connects in a row work?

I would be surprised if a popular chip like the STM32H5 series would be that broken in a generic way but nobody else ran into and reported it.

Are you 100% sure that it was ONLY the J-Link version you changed and not also the target application that changed, which now maybe switches the debug pins to GPIO by accident or similar?

florentb · September 9, 2023 at 5:50 PM

Yes, it is working first time on JLink 7.68.
It is the exact same board, with the same JTrace, and exactly the same connections (the only change is the JLink software).

Code

λ jlink                                                               
SEGGER J-Link Commander V7.68 (Compiled Jul 14 2022 16:56:10)         
DLL version V7.68, compiled Jul 14 2022 16:54:28                      
Connecting to J-Link via USB...O.K.                                   
Firmware: J-Trace PRO V2 Cortex-M compiled Jun  6 2023 10:51:16       
Hardware version: V2.00                                               
J-Link uptime (since boot): 0d 00h 27m 42s                            
S/N: 752001898                                                        
License(s): RDI, FlashBP, FlashDL, JFlash, GDB                        
USB speed mode: Super speed (5 GBit/s)                                
IP-Addr: DHCP (no addr. received yet)                                 
Emulator has RAWTRACE capability                                      
VTref=1.826V                                                          
Type "connect" to establish a target connection, '?' for help         
J-Link>connect                                                        
Please specify device / core. <Default>: EFR32BG22CXXXF352            
Type '?' for selection dialog                                         
Device>STM32H730IB                                                    
Please specify target interface:                                      
  J) JTAG (Default)                                                   
  S) SWD                                                              
  T) cJTAG                                                            
TIF>s                                                                 
Specify target interface speed [kHz]. <Default>: 4000 kHz             
Speed>                                                                
Device "STM32H730IB" selected.                                        
Connecting to target via SWD                                          
ConfigTargetSettings() start                                          
ConfigTargetSettings() end                                            
Found SW-DP with ID 0x6BA02477                                        
STM32 (connect): Can not attach to CPU. Trying connect under reset.   
Found SW-DP with ID 0x6BA02477                                        
Active write protected STM32 device detected.                         
This could cause problems during flash download.                      
Note: Unsecuring will trigger a mass erase of the internal flash.     
Executing default behavior previously saved in the registry.          
Device will be unsecured now.                                         
Found SW-DP with ID 0x6BA02477                                        
DPIDR: 0x6BA02477                                                     
CoreSight SoC-400 or earlier                                          
Scanning AP map to find all available APs                             
AP[3]: Stopped AP scan as end of AP map has been reached              
AP[0]: AHB-AP (IDR: 0x84770001)                                       
AP[1]: AHB-AP (IDR: 0x84770001)                                       
AP[2]: APB-AP (IDR: 0x54770002)                                       
Iterating through AP map to find AHB-AP to use                        
AP[0]: Core found                                                     
AP[0]: AHB-AP ROM base: 0xE00FE000                                    
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)              
Found Cortex-M7 r1p2, Little endian.                                  
FPUnit: 8 code (BP) slots and 0 literal slots                         
CoreSight components:                                                 
ROMTbl[0] @ E00FE000                                                  
[0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table                  
ROMTbl[1] @ E00FF000                                                  
[1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7                     
[1][1]: E0001000 CID B105E00D PID 000BB002 DWT                        
[1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7                     
[1][3]: E0000000 CID B105E00D PID 000BB001 ITM                        
[0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7                     
[0][2]: E0043000 CID B105900D PID 004BB906 CTI                        
Cache: Separate I- and D-cache.                                       
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way                     
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way                     
Cortex-M7 identified.                                                 
J-Link>

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However, I am using the JTrace Pro, which I suspect not many people are using, so it may be broken since quite a long time.

Thanks,
Florent

SEGGER - Fabian · September 11, 2023 at 8:32 AM

Hi Florent,
I just gave this a quick try on the STM32H735G-DK (STM32H735).
I could not test it on an STM32H730, as there are no evaluation boards available as far as I know,
but both should behave the same from a debug standpoint.

On our side it worked without any issues with J-Trace Pro V2 Cortex-M (see below).

Do you have any target application running on your device?
If so, does the same issue appear after erasing & power-cycling the device?

Best regards,
Fabian

Code

Firmware: J-Trace PRO V2 Cortex-M compiled Jun  6 2023 10:51:16
Hardware version: V2.00
J-Link uptime (since boot): 0d 00h 00m 01s
S/N: 752060000
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
USB speed mode: High speed (480 MBit/s)
IP-Addr: DHCP (no addr. received yet)
Emulator has RAWTRACE capability
VTref=3.307V
Device "STM32H730IB" selected.




Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 15us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
InitTarget() end - Took 7.04ms
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x84770001)
AP[1]: AHB-AP (IDR: 0x84770001)
AP[2]: APB-AP (IDR: 0x54770002)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FE000
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
Cache: L1 I/D-cache present
Found Cortex-M7 r1p2, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FE000
[0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[1][1]: E0001000 CID B105E00D PID 000BB002 DWT
[1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[1][3]: E0000000 CID B105E00D PID 000BB001 ITM
[0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[0][2]: E0043000 CID B105900D PID 004BB906 CTI
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M7 identified.

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