[SOLVED] Cortex-A7 FPU registers D16-D31 wrongly displayed

Hello!
Using latest Ozone (v3.38a) debugging .elf application for IMX6ULL (Cortex-A7), the second part of double precision registers (D16 to D31) are displayed incorrectly:

It seems only lower 32 bits of the double register is intact, but high 32 bits are zeroed out for some reason.
This is user interface only issue, registers contents are actually right and CPU execution goes as intended.

In the J-Link web control panel these registers are fine with full 64 bit data:

In IAR EW debugger all is fine also - double precision registers D0-D31 are displayed and edited OK.

Regards, Vlad.

Hello, Alex.
Yes, indeed i'am using .svd file from Ozone installation: C:/Program Files/SEGGER/Ozone V3.38a/Config/CPU/Cortex-A7.svd

Board i'am working with is MYS-6ULX Single Board Computer from MYIR, i don't have any evaluation board, sorry.

.log file is attached.
Which is strange - in the log the D registers are seems to read fine in full 64 bits (and D29 is named as D39 for some reason):

D16=0x0008000000200000
D17=0x00
D18=0x0008000000200000
D19=0x0002000000040000
D20=0x80001C0E80001C0E
D21=0x80001C0E80001C0E
D22=0x8FD01C0E8FC01C0E
D23=0x8FF01C0E8FE01C0E
D24=0x0CD004160CC00416
D25=0x0CF004160CE00416
D26=0x0D1004160D000416
D27=0x0D3004160D200416
D28=0x0D5004160D400416
D39=0x0D7004160D600416
D30=0x0D9004160D800416
D31=0x0DB004160DA00416

And the screenshots:

PS: attached board initialization script, in case it might be helpful.

Regards,
Vlad.

Thanks, Alex.
I hope fixing that issue does not take much time

Thanks a lot, Alex!
That is a real pleasure using your software!