[ANSWERED] JTAG Pullups on STMICRO Cortex-M3 and NRESET Operation

Schatzy · November 5, 2009 at 5:55 PM

I am having trouble downloading code into my STM32F103ZC application.

Does anybody have any suggestions? I could use JTAG or SWD...

I get parity errors before any download activity might occur. Could there be a problem with the NRESET interface between the JLINK and the processor?

I have seen people suggest pullups in the JTAG interface wiring, but I am guessing that 10K is the value to use and that all the JTAG lines get pulled up except the TCLK which gets pulled down. Can anybody tell me what is happening? I thought that the Jlink applies a reset to the processor so that the JTAG lines operate with internal pullup/pulldwn.

Should NRESET get a pullup too?

SEGGER - Rolf · November 28, 2009 at 3:28 PM

Hello,

as a general rule: Simply copy this part of the schematic from the eval board.
And of course: Get an eval board. Does not cost much, but this way you have a stable platform
for first experiments. And if you copy the relevant parts of the schematics, you hardware should work the
same way.

Reg. Pull-ups: NRESET should always have one, and typically also TCK. But again: follow what the experts
do on an eval board. Some processors have built-in pull ups, so it does not hurt to read the manual.

Best regards,
Rolf

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