[SOLVED/OR] How does SWO Viewer measure the core frequency?

Hi,

How does SWO Viewer measure the core frequency?

Is the measured output available on stdout as well ?

regards

Hi Niklas,

thanks for your answer.

how is the measurement done?

basically I want to know because I would like to judge if I can trust that reading.

I'm in doubt if my controller is running at the correct frequency.

I'm using a STM32F429 device.

J-Link Commander says 180 MHz. This covers with my intention.

But I face some strange effects with my application and want to be sure about the Freq.

I'm on linux. there is no binary called "JLinkCommander". But "JLinkExe" seems to understand the same commands.
How would I connect to a target via script mode?

I want to have the core frequency printed on stdout.

edit:
hope this helps if someone wants to do the same:

[developer@localhost ~]$ cat cpu_freq 
eoe 1
testcspeed 0x20000000
q

[developer@localhost ~]$ /usr/local/bin/JLinkExe -device STM32F429VG -if swd -speed 6000 -CommanderScript cpu_freq
SEGGER J-Link Commander V5.10k (Compiled Feb 9 2016 18:31:25)
DLL version V5.10k, compiled Feb 9 2016 18:31:20




Script file read successfully.
Processing script file...


J-Link Commander will now exit on Error


J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: J-Trace Cortex-M Rev.3 compiled Sep 4 2015 18:16:12
Hardware version: V3.10
S/N: xxxxxxxxxxxxx
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
Emulator has Trace capability
VTref = 3.293V
Target connection not established yet but required for command.
Device "STM32F429VG" selected.




Found SWD-DP with ID 0x2BA01477
Found SWD-DP with ID 0x2BA01477
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl 0 @ E00FF000
ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS
ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
Testing CPU clock frequency @ address 0x20000000...
CPU running at 180051 kHz




Script processing completed.

with some grep magic I get the CPU freq on stdout:

[developer@localhost ~]$ /usr/local/bin/JLinkExe -device STM32F429VG -if swd -speed 6000 -CommanderScript cpu_freq | grep -oP '\d+(?= kHz)'
180051

thanks

Hi Niklas,

thank you very much for your explanation!
I appreciate it very much!

I have edited a previous post of mine.

best regards
Peter

just a quick note:

one has to be really careful on what memory address is specified for the "testcspeed" command in JLink Commander.
for Freescale (NXP) devices there are different SRAM regions which are accessible differently for data and instructions.

I was confused because I got a reading of half the frequency I was expecting.

turns out, I was running the test in a suboptimal SRAM region (SRAM_U).

The information in which memory region the speed test should be run is available in JLinkSWO Viewer.

Suggestion: use this information in JLinkCommander when no address information is given.

from http://cache.nxp.com/files/microcon…note/AN4745.pdf :

Quote

The memory itself can be accessed in a single cycle, but because instruction accesses to the system bus incurs a one clock delay at the core, SRAM_U instruction accesses take at least two clocks.