Clarification on JLink operation when writing while core is not aborted

  • Hi

    Is it mandatory for the A9 core to be aborted before writing to an address or a core register?

    we noticed that if we attempt to write to a register or any address while the core is running the writing is performed successfully however the core state is halted.
    We also see that if interrupts were enabled in the CPSR register, after the write the CPSR interrupt state is now disabled.

    We are using jlink SDK for Core\Host communication. The workaround we found is to add Abort before each operation and run afterwards.

    Is this the expected behavior?

    Thanks!
    Hila

  • Hi Hila,

    Quote

    Is it mandatory for the A9 core to be aborted before writing to an address or a core register?


    I think you mean "is halted" here (a very common term in debugging...). "Abort" is something different, usually indicating a failed memory access.

    Rules for Cortex-A:
    Memory cannot be written/read while the CPU is running. Unlike on Cortex-M, accesses via the AHB-AP while the core is running, are not possible, since they bypass the caches, which would cause immense problems.
    Moreover, the AHB-AP needed for this, is not present on all Cortex-A devices. It is up to the chip vendor to implement it or not (for Cortex-A)
    CPU registers cannot be read/written while the CPU is running. This applies to *any* CPU and it makes no sense at all to write them while the CPU is running.

    For J-Link:
    If you try to write/read memory on a Cortex-A9 while the CPU is running, J-Link will temporarily halt the CPU, perform the memory access and restarts the CPU.
    There was a problem in earlier versions of the DLL, that the CPU was not restarted after the access, in some situations, but this has been corrected in V4.92


    - Alex

    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: https://www.segger.com/ticket/

    Or you can contact us via e-mail.

  • Hello Alex,

    Thanks you for your response and for you explanation.

    I moved to version 492, indeed the core is re-run after the read/write commands however I had quite a lot of problems when reading or modifying CSPR register thru the SDK.
    .. I wonder if it's because of these fixes or perhaps I'm misusing it

    To be on teh safe side, I added to our automatic system a Halt \ run command before read\write.

    Thanks again,

    Hila

  • Hi Hila,

    Thanks for the feedback.
    Regarding the CPSR: What kind of problems? Can you provide an example sequence including the resulting error?


    - Alex

    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: https://www.segger.com/ticket/

    Or you can contact us via e-mail.

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