Cortex-A7 FPU registers D16-D31 wrongly displayed

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    • Cortex-A7 FPU registers D16-D31 wrongly displayed

      New

      Hello!
      Using latest Ozone (v3.38a) debugging .elf application for IMX6ULL (Cortex-A7), the second part of double precision registers (D16 to D31) are displayed incorrectly:


      It seems only lower 32 bits of the double register is intact, but high 32 bits are zeroed out for some reason.
      This is user interface only issue, registers contents are actually right and CPU execution goes as intended.

      In the J-Link web control panel these registers are fine with full 64 bit data:


      In IAR EW debugger all is fine also - double precision registers D0-D31 are displayed and edited OK.

      Regards, Vlad.

    • New

      Hi Vlad,
      thanks for letting us know. We are not aware of such an issue.
      Which SVD file are you using? Is it `Cortex-A7.svd` that is coming with Ozone? Are you able to reproduce the issue on an eval board? If so: which one? Could you please provide a J-Link log recorded during a debug session where the issue is reproduced? The register window should show, a in your screenshot, both some registers where the display is correct (i.e. D0..D15) as well as registers where the display is incorrect (i.e. D16..D31). Could you also please provide a screenshot where the register content is displayed as hex value?
      Best regards
      -- AlexD
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