Setup SystemView with FreeRTOS in IAR

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    • Setup SystemView with FreeRTOS in IAR

      I work on a project which uses Renesas RA6M5 MCU. The FreeRTOS version is 10.4.3. We use IAR 9.10. I installed the latest version of JLink V798a. The SystemView version is V3.54.

      I'm trying to setup the Segger SystemView with FreeRTOS. I followed wiki.segger.com/FreeRTOS_with_SystemView. I also followed the document "UM08027.pdf".

      Here are what I did:
      1. After Segger SystemView software installed. Copy these folders to my project:
      C:\Program Files\SEGGER\SystemView\Src\Config -> myProject\Segger\SystemView\Config
      C:\Program Files\SEGGER\SystemView\Src\Sample\FreeRTOSV10.4 -> myProject\Segger\SystemView\FreeRTOS
      C:\Program Files\SEGGER\SystemView\Src\SEGGER -> myProject\Segger\SystemView\Source

      2. Add these files in the IAR project. Please see attached "Segger_Integration_Files.png":
      /Config/Global.h
      /Config/SEGGER_RTT_Conf.h
      /Config/SEGGER_SYSVIEW_Conf.h
      /FreeRTOS/Config/Cortex-M/SEGGER_SYSVIEW_Config_FreeRTOS.c
      /FreeRTOS/SEGGER_SYSVIEW_FreeRTOS.c
      /FreeRTOS/SEGGER_SYSVIEW_FreeRTOS.h
      /Source/SEGGER.h
      /Source/SEGGER_RTT.c
      /Source/SEGGER_RTT.h
      /Source/SEGGER_RTT_ASM_ARMv7M.S
      /Source/SEGGER_RTT_printf.c
      /Source/SEGGER_SYSVIEW.c
      /Source/SEGGER_SYSVIEW.h
      /Source/SEGGER_SYSVIEW_ConfDefaults.h
      /Source/SEGGER_SYSVIEW_Int.h

      3. Add the files path in the project options:
      Project->Options->Runtime Checking->C/C++ Compiler->Preprocessor
      Project->Options->Runtime Checking->Assembler->Preprocessor

      4. At the end of FreeRTOSConfig.h or before every "FreeRTOS.h" add

      Source Code

      1. #include "SEGGER_SYSVIEW_FreeRTOS.h"
      5. Update the configurations:
      5.1) Change: configUSE_TRACE_FACILITY 1
      5.2) Change SEGGER_SYSVIEW_ConfDefaults.h: SEGGER_SYSVIEW_RTT_BUFFER_SIZE (1024*5)
      5.3) In SEGGER_SYSVIEW_Config_FreeRTOS.c

      Source Code

      1. #define SYSVIEW_APP_NAME "FreeRTOS My Device"
      2. #define SYSVIEW_DEVICE_NAME "My Device"
      3. #define SYSVIEW_RAM_BASE (0x20000000)


      5.4) From the definition, the SEGGER_SYSVIEW_CORE is SEGGER_SYSVIEW_CORE_CM3. But MCU is Renesas R7FA6M5AH, which is Cortex-M33. But I don't see any definition for Cortex-M33. Is it okay to have SEGGER_SYSVIEW_CORE as SEGGER_SYSVIEW_CORE_CM3 for my MCU?

      6. Apply the Git path:
      6.1) In the path file line #9, there is no INCLUDE_pxTaskGetStackStart. But I added "#define INCLUDE_pxTaskGetStackStart 1"
      6.2) Maybe because I'm using the FreeRTOS from Renesas, I don't have "FreeRTOS/Source/portable/GCC/ARM_CM0/port.c", "FreeRTOS/Source/portable/GCC/ARM_CM3/port.c", or "FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c". Therefore, I don't have "xPortSysTickHandler()". But I have "Renesas\fsp_3.5.0\ra\fsp\src\rm_freertos_port\port.c". So I changed "void SysTick_Handler (void)" to apply the line #108 - #120.
      6.3) For the same reason, I don't have "FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h", "FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h", or "FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h". But I do have "Renesas\fsp_3.5.0\ra\fsp\src\rm_freertos_port\portmacro.h". So I added:

      Source Code

      1. // I have to add these in order to get it compile:
      2. #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
      3. #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
      5. #define portEND_SWITCHING_ISR( xSwitchRequired ) { if( xSwitchRequired ) \
      6. { traceISR_EXIT_TO_SCHEDULER(); portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } else { traceISR_EXIT(); } }


      6.4) For line #210, I can't find "void prvAddNewTaskToReadyList(". But I found the statements in "void vTaskSuspend( TaskHandle_t xTaskToSuspend )". So I added these. Not sure if I did it correctly or not:
      traceMOVED_TASK_TO_SUSPENDED_LIST(pxTCB);

      7. Add the following code before the task creations and "vTaskStartScheduler()":
      SEGGER_SYSVIEW_Conf();
      SEGGER_SYSVIEW_Start();

      After the above changes, I got the build passed. So I started my firmware and then paused it. I checked _SEGGER_RTT. I tried to export the data. But there is no way in IAR to export the data as "Raw Binary". I can't save it as SVdat format. Please see attached "IAR_Save_Memory.png". How can I export the memory data as binary in IAR?

      I also tried to get the Continuous Recording working. In SystemView, I configured the JLink. Please see attched "Segger_SystemView_RecorderConfig.png". I hit the "Start Recording" button. After running 1% for a couple of seconds, the execution stopped. There is nothing showing up in the SystemView. Could you please point out where I did it wrong?

      Thanks in advance!
      Images

      • Segger_Integration_Files.png

        13 kB, 448×326, viewed 117 times

      • IAR_Save_Memory.png

        11.97 kB, 376×266, viewed 127 times

      • Segger_SystemView_RecorderConfig.png

        9.11 kB, 382×469, viewed 125 times

      The post was edited 1 time, last by pilot8 ().

    • Hi,

      I am also in similar situation. Also using FreeRTOS 10.4.3. I've been able to get some information back from the device before the SystemView (v3.54) crashes. See profile_log.PNG attached.

      One thing to add, is that I had to manually add

      C Source Code

      1. #define RTT_USE_ASM (0)



      to SEGGER_RTT_Config.h because it could not link the `.S` for ARMV7, since I am using Renesas R7FA6M5BH which is ARMV8, I thought that would be ok. I found this here (link).

      I can compile and run my FreeRTOS application, but cannot understand why the SystemViewer is crashing. If anyone from SEGGER could give some insights that would be very much appreciated. I have attached the crash log from Windows. WERF4A2.tmp.WERInternalMetadata.xml

      The application seems to crash after some data has been received from the FreeRTOS via J-Link. I have found that in the Recorder Configuration, I need to tell where the RTT Control Block is, so I just point it to the location in RAM (0x20000B3C).

      Regarding the patching steps, I went through the patch file manually and made the changes myself to the required files. Primarily because the project is not using e2 IDE and instead uses custom build using CMake.

      Like you said, I also don't have the CM3/CM4 ports header files. I just see one matching file port.c that says

      C Source Code

      1. /*-----------------------------------------------------------
      3. * Implementation of functions defined in portable.h for RA MCUs
      5. *----------------------------------------------------------*/
      I have followed steps from this SEGGER guide (link).

      The only way I can get data out, is to flash my .elf using Ozono, start the application, Disconnect Ozone from target. Start SystemView, configure Recorder, click Run. I can see some data for a short period of time before the application crashes.

      Just to add, this is what I see in the SystemView Log tab

      C Source Code

      1. 14:50:18 - JLink: Device "R7FA6M5BH" selected.
      2. 14:50:18 - JLink: ConfigTargetSettings() start
      3. 14:50:18 - JLink: Configuring FlashDLNoRMWThreshold=0x200 in order to make sure that option bytes programming is done via read-modify-write
      4. 14:50:18 - JLink: ConfigTargetSettings() end - Took 10.1ms
      5. 14:50:18 - JLink: InitTarget() start
      6. 14:50:18 - JLink: SWD selected. Executing JTAG -> SWD switching sequence.
      7. 14:50:18 - JLink: DAP initialized successfully.
      8. 14:50:18 - JLink: Determining TrustZone configuration...
      9. 14:50:18 - JLink: Secure Debug: Enabled (SSD)
      10. 14:50:18 - JLink: Determining currently configured transfer type by reading the AHB-AP CSW register.
      11. 14:50:18 - JLink: --> Correct transfer type configured. Done.
      12. 14:50:18 - JLink: InitTarget() end - Took 54.4ms
      13. 14:50:18 - JLink: Found SW-DP with ID 0x6BA02477
      14. 14:50:18 - JLink: DPIDR: 0x6BA02477
      15. 14:50:18 - JLink: CoreSight SoC-400 or earlier
      16. 14:50:18 - JLink: Scanning AP map to find all available APs
      17. 14:50:18 - JLink: AP[2]: Stopped AP scan as end of AP map has been reached
      18. 14:50:18 - JLink: AP[0]: AHB-AP (IDR: 0x84770001)
      19. 14:50:18 - JLink: AP[1]: APB-AP (IDR: 0x54770002)
      20. 14:50:18 - JLink: Iterating through AP map to find AHB-AP to use
      21. 14:50:18 - JLink: AP[0]: Core found
      22. 14:50:18 - JLink: AP[0]: AHB-AP ROM base: 0xE00FE000
      23. 14:50:18 - JLink: CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
      24. 14:50:18 - JLink: Feature set: Mainline
      25. 14:50:18 - JLink: Cache: No cache
      26. 14:50:18 - JLink: Found Cortex-M33 r0p4, Little endian.
      27. 14:50:18 - JLink: FPUnit: 8 code (BP) slots and 0 literal slots
      28. 14:50:18 - JLink: Security extension: implemented
      29. 14:50:18 - JLink: Secure debug: enabled
      30. 14:50:18 - JLink: CoreSight components:
      31. 14:50:18 - JLink: ROMTbl[0] @ E00FE000
      32. 14:50:18 - JLink: [0][0]: E0044000 CID B105900D PID 005BB906 DEVARCH 00000000 DEVTYPE 14 CTI (?)
      33. 14:50:18 - JLink: [0][1]: E0047000 CID B105900D PID 003BB908 DEVARCH 00000000 DEVTYPE 12 CSTF
      34. 14:50:18 - JLink: [0][2]: E0048000 CID B105900D PID 001BB961 DEVARCH 00000000 DEVTYPE 21 ETB
      35. 14:50:19 - JLink: [0][3]: E0049000 CID B105F00D PID 001BB101 TSG
      36. 14:50:19 - JLink: [0][4]: E0040000 CID B105900D PID 000BBD21 DEVARCH 00000000 DEVTYPE 11 TPIU
      37. 14:50:19 - JLink: [0][5]: E00FF000 CID B105100D PID 000BB4C9 ROM Table
      38. 14:50:19 - JLink: ROMTbl[1] @ E00FF000
      39. 14:50:19 - JLink: [1][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
      40. 14:50:19 - JLink: [1][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
      41. 14:50:19 - JLink: [1][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
      42. 14:50:19 - JLink: [1][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
      43. 14:50:19 - JLink: [1][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
      44. 14:50:19 - JLink: [1][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
      45. 14:50:19 - JLink: Memory map 'after startup completion point' is active
      46. 14:50:19 - Warning: RTT host buffer overflow. Data has been lost.
      47. 14:50:19 - Warning: Recorder encountered an error. Recording stopped.
      48. 14:50:19 - ERROR: Error while recording. Recorder stopped.
      49. 14:50:19 - Warning: Error (-162) during record analysis
      Display All

      Would like to resolve this crashing issue to evaluate the tool more properly.

      Thanks
      Images

      • recorder_config.PNG

        11.13 kB, 381×496, viewed 98 times

      • profile_log.PNG

        283.84 kB, 1,343×728, viewed 129 times

      The post was edited 1 time, last by dnars: added dump from log window ().