Can not halt m4 on AM572x evaluation module by JTrace.

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    • Connecting to target via cJTAG
      InitTarget() start
      TI AM572x (Cortex-M4_0 core) J-Link script
      J-Link script: Init ICEPick
      TotalIRLen = 6, IRPrint = 0x01
      InitTarget() end - Took 96.1ms
      TotalIRLen = 10, IRPrint = 0x0011
      JTAG chain detection found 2 devices:
      #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
      #1 Id: 0x2B99002F, IRLen: 06, TI ICEPick
      DPv0 detected
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[1]: APB-AP (IDR: Not set)
      AP[2]: JTAG-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.
      FPUnit: 6 code (BP) slots and 2 literal slots
      CoreSight components:
      ROMTbl[0] @ E00FF000
      [0][0]: E000E000 CID B105E00D PID 000BB000 SCS
      [0][1]: E0001000 CID B105E00D PID 003BB002 DWT
      [0][2]: E0002000 CID B105E00D PID 002BB003 FPB
      [0][3]: E0000000 CID 00000000 PID 00000000 ???
      [0][4]: E0040000 CID 00000000 PID 00000000 ???
      [0][6]: E0042000 CID 00000000 PID 00000000 ???
      Memory zones:
      Zone: "Default" Description: Default access mode
      Cortex-M4 identified.
      J-Link>
      J-Link>halt
      CPU could not be halted


      Anyone can help me ?


      Best regards,
      Steve Sun

    • Hi Steve,

      Sounds a bit like the M4 is clocked, so the AHB-AP debug domain is accessible but the core itself is still held in reset.
      This would explain why it is not responding to halt requests etc.

      Is that possible in your case?
      Please read the forum rules before posting.

      Keep in mind, this is *not* a support forum.
      Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
      Should you be entitled to support you can contact us via our support system: segger.com/ticket/
      Or you can contact us via e-mail.

    • Hi, Alex

      Thanks very much. It seems that what you said makes sense, but I'm NOT sure.

      What is your suggestion？ I can try on my board. My board is a official board, AM572x evaluation module.
      ti.com/tool/TMDSEVM572X

      My JTrace is a official genuine product and I have update it to the latest firmware.

      Maybe, you can have a look at this page below, you can find someting.

      e2e.ti.com/support/processors-…ect-ipu-by-jtrace/5199757?
      If you want more information, let me know and I will paste it here.

      I have been trying for a few days now, but there is no solution.


      Best regards,
      Steve Sun

    • Hi Steven,

      I see that you have been in touch with Richard W. at TI. A very capable guy…
      Pretty sure he can help you out.

      As J-Link’s Cortex-M4 support is generally working and we are not talking about an issue with our flash algo etc. but a connect works and a simple halt command is not accepted / acknowleged by the core, it can only be something chip-specific like the M4 being held in reset.

      My suggestion is to get one of TI’s example projects up and running that blinks an LED or so on the M4. Then modify the project into something like “turn LED on and enter endless loop” (something that does not go into any low power modes for sure, as these can also interfere with debug!)
      Please read the forum rules before posting.

      Keep in mind, this is *not* a support forum.
      Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
      Should you be entitled to support you can contact us via our support system: segger.com/ticket/
      Or you can contact us via e-mail.