Hi. The Chip I'm working on doesn't have a ROM. So I have a need to halt the core to prevent uninitialized code from executing. I HALT the core in "InitTarget()" but then after "feature detection" the core is resumed. See Log below. It doesn't appear I have the hook to halt the core again until "SetupTarget()". OpenOCD will put the core back into the halt state after "examine" if the core was halted before examine. As Well, I'd like to be able to set the riscV reset type, How do I do this? The log file indicates "JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)". Thank you

T29398 004:801.411 Temp. halting CPU for for feature detection...
T29398 004:819.112 HW instruction/data BPs: 1
T29398 004:819.213 Support set/clr BPs while running: No
T29398 004:822.481 HW data BPs trigger before execution of inst
T29398 004:823.533 CSR access via abs. commands: Yes
T29398 004:823.599 Compressed instruction support: Yes
T29398 004:823.651 Feature detection done. Restarting core...
T29398 004:826.061 BG memory access support: Via SBA
T29398 004:826.133 SetupTarget() start
T29398 004:826.185 J-Link Script File: Executing SetupTarget()
T29398 004:839.569 Target is halted!
T29398 004:839.679 SetupTarget() end - Took 13.4ms

Note, regarding halt for debug, we have logic to prevent the core from fetching instructions after core reset de-assert. The first instruction that will be fetched after reset de-assert will be from the debug ROM upon the initial halt in "InitTarget" before "feature detect"