On the wiki page wiki.segger.com/QSPI_Flash_Programming_Support it states, "SEGGERs SPIFI flash loaders preserve the status of the QE bit before flash programming and restores it to the same state afterwards." I believe this was meant to say that the QE bit would first be read from the QSPI flash and restored upon completing any operations that access the QSPI flash. We have found that this is not true when targeting an MCU with an attached IS25WP256D QSPI flash. The steps that I'm using to reproduce this are:

1. Erase and program the QSPI flash using J-Link commander or J-Flash Lite and program the QSPI flash.
2. Load and run an application in the MCU's internal flash that sets the Quad Enable bit.
3. Attempt to again erase the QSPI flash using J-Link command or J-Flash Lite.

This final step will fail as shown below. In my case I'm only erasing the first 0x100000 bytes of the QSPI flash :

J-Link>erase 0x4000000 0x4100000
'erase': Performing implicit reset & halt of MCU.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Erasing selected range...

****** Error: Failed to prepare RAMCode using RAM
Error while determining flash info (Bank @ 0x04000000)
ERROR: Erase returned with error code -1.
J-Link>

Once this failure is seen I can run a separate application in the MCU internal flash that disables the QE bit to put the QSPI flash back into single SPI mode. After doing this I'm once again able to erase and program the QSPI flash using either J-Link Commander or J-Flash Lite. So I am able to work around the issue, but this is extremely cumbersome.

Is there currently any way to set/clear the QE bit in the external flash manually using the J-Link? Will an update to the Segger software be required in order for the QE bit state to be managed as advertised on the wiki page?

For context, the MCU is a cortex-m4, Microchip ATSAME54P20A.
Currently I'm using J-Link v7.82b.

Thanks.