Hi Team,
We have a SOC where we have multiple Cortex-A53 core and Cortex-M series CPU. I am able to connect the M0 CPU using custom connect sequence by defining in JLinkScript. However i am not able to connect the Cortex-A53 even though, JLink can find the CPU and its information, it fails at halting CPU state.
We also have few Lauterbach and we don't see the problem there when connecting to Cortex-A53.
DPIDR: 0x4C013477
CoreSight SoC-600 or later (DPv3 detected)
AP map detection skipped. User specified AP map and usage.
Using preconfigured AP[0] as APB-AP
AP[0]: APB-AP found
Scanning ROMTbl @ 0x00000000
[0]Comp[0] @ 0x00001000: CSTF
[0]Comp[1] @ 0x00002000: ETB
[0]Comp[2] @ 0x00003000: CSS600-CTI
[0]Comp[3] @ 0x00004000: CSS600-TSG
[0]Comp[4] @ 0x00800000: ROM Table
Scanning ROMTbl @ 0x00800000
[1]Comp[0] @ 0x00810000: Cortex-A53
[1]Comp[1] @ 0x00820000: CSS600-CTI
Core found. Stopped ROM table scan: wiki.segger.com/ROMTableScan
Cortex-A53 @ 0x00810000 (detected)
CoreCTI @ 0x00820000 (detected)
Debug architecture: ARMv8.0
6 code breakpoints, 4 data breakpoints
Processor features:
EL0 support: AArch64 + AArch32
EL1 support: AArch64 + AArch32
EL2 support: AArch64 + AArch32
EL3 support: AArch64 + AArch32
FPU support: Not implemented
Add. info (CPU temp. halted)
CPU could not be halted
Failed to temporarily halt CPU
Connect failed.
And following is JLinkScript configuration
int ConfigTargetSettings(void) {
CPU = CORTEX_A53;
JTAG_Speed = 1000; // 1MHz
JTAG_AllowTAPReset = 0; // Not allowed top enter JTAG TAP reset
// Coresight Access Ports
JLINK_ExecCommand("CORESIGHT_AddAP = Index=0 Type=APB-AP Addr=0xXXXXXXXX");
JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AXI-AP Addr=0xXXXXXXXX");
JLINK_ExecCommand("CORESIGHT_SetIndexBGMemAPToUse = 1");
JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 0");
return 0;
}
void ResetTarget(void) {
}
/**********************************************************************************************
*
* InitTarget
*
* Notes
* (1) High-level functions like MEM_xxx functions must not be used here.
* They may only be used in SetupTarget() which is called later in the
* connect process.
*/
void InitTarget(void) {
// Report("J-Link script: Init");
_set_tap_chain();
_read_dp_idr();
//-------------------------------------------------------------------------
// Define DAP TAP as slave.
//-------------------------------------------------------------------------
// TAP chain is: TDI -> Master TAP (5-bits IRLen) -> DAP TAP (4-bits IRLen) ->
// TDO
JTAG_DRPre = 0;
JTAG_DRPost = 1;
JTAG_IRPre = 0;
JTAG_IRPost = 5;
JTAG_IRLen = 4;
}
Is there any other sequence required for halting Cortex-A53 CPU?
We have a SOC where we have multiple Cortex-A53 core and Cortex-M series CPU. I am able to connect the M0 CPU using custom connect sequence by defining in JLinkScript. However i am not able to connect the Cortex-A53 even though, JLink can find the CPU and its information, it fails at halting CPU state.
We also have few Lauterbach and we don't see the problem there when connecting to Cortex-A53.
DPIDR: 0x4C013477
CoreSight SoC-600 or later (DPv3 detected)
AP map detection skipped. User specified AP map and usage.
Using preconfigured AP[0] as APB-AP
AP[0]: APB-AP found
Scanning ROMTbl @ 0x00000000
[0]Comp[0] @ 0x00001000: CSTF
[0]Comp[1] @ 0x00002000: ETB
[0]Comp[2] @ 0x00003000: CSS600-CTI
[0]Comp[3] @ 0x00004000: CSS600-TSG
[0]Comp[4] @ 0x00800000: ROM Table
Scanning ROMTbl @ 0x00800000
[1]Comp[0] @ 0x00810000: Cortex-A53
[1]Comp[1] @ 0x00820000: CSS600-CTI
Core found. Stopped ROM table scan: wiki.segger.com/ROMTableScan
Cortex-A53 @ 0x00810000 (detected)
CoreCTI @ 0x00820000 (detected)
Debug architecture: ARMv8.0
6 code breakpoints, 4 data breakpoints
Processor features:
EL0 support: AArch64 + AArch32
EL1 support: AArch64 + AArch32
EL2 support: AArch64 + AArch32
EL3 support: AArch64 + AArch32
FPU support: Not implemented
Add. info (CPU temp. halted)
CPU could not be halted
Failed to temporarily halt CPU
Connect failed.
And following is JLinkScript configuration
int ConfigTargetSettings(void) {
CPU = CORTEX_A53;
JTAG_Speed = 1000; // 1MHz
JTAG_AllowTAPReset = 0; // Not allowed top enter JTAG TAP reset
// Coresight Access Ports
JLINK_ExecCommand("CORESIGHT_AddAP = Index=0 Type=APB-AP Addr=0xXXXXXXXX");
JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AXI-AP Addr=0xXXXXXXXX");
JLINK_ExecCommand("CORESIGHT_SetIndexBGMemAPToUse = 1");
JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 0");
return 0;
}
void ResetTarget(void) {
}
/**********************************************************************************************
*
* InitTarget
*
* Notes
* (1) High-level functions like MEM_xxx functions must not be used here.
* They may only be used in SetupTarget() which is called later in the
* connect process.
*/
void InitTarget(void) {
// Report("J-Link script: Init");
_set_tap_chain();
_read_dp_idr();
//-------------------------------------------------------------------------
// Define DAP TAP as slave.
//-------------------------------------------------------------------------
// TAP chain is: TDI -> Master TAP (5-bits IRLen) -> DAP TAP (4-bits IRLen) ->
// TDO
JTAG_DRPre = 0;
JTAG_DRPost = 1;
JTAG_IRPre = 0;
JTAG_IRPost = 5;
JTAG_IRLen = 4;
}
Is there any other sequence required for halting Cortex-A53 CPU?
Thanks,
Ashish
Ashish
The post was edited 2 times, last by axiado1864 ().