[ABANDONED] RISC-V Hart selection and CSR values

  • [ABANDONED] RISC-V Hart selection and CSR values

    When connecting to a RISC-V board with 5 cores (on two JTAG chains), how do we select which HART will be accessed? Someone has a configuration file which supposedly selects HART 3, but the "mhartid" register shows 0 when using that config. The other CSR register values do not look correct either.

    OpenOCD, on the other hand, sees all 5 cores and creates targets for each. Each target reports the proper "mhartid", and the "misa" registers look correct.

    As OpenOCD can see the correct values, it would appear that JLink is connected properly and the device is working. So what might be wrong with the JLink config? Can someone please give troubleshooting advice?

    Here is JLink's output.

    Source Code

    1. License(s): FlashBP, GDB
    2. USB speed mode: Full speed (12 MBit/s)
    3. VTref=3.299V
    4. Device "U74-MC" selected.
    7. Connecting to target via JTAG
    8. ConfigTargetSettings() start
    9. ConfigTargetSettings() end - Took 5us
    10. InitTarget() start
    11. InitTarget() end - Took 3us
    12. TotalIRLen = 10, IRPrint = 0x0021
    13. JTAG chain detection found 2 devices:
    14. #0 Id: 0x07110CFD, IRLen: 05, Unknown device
    15. #1 Id: 0x07110CFD, IRLen: 05, Unknown device
    16. Debug architecture:
    17. RISC-V debug: 0.13
    18. AddrBits: 7
    19. DataBits: 32
    20. IdleClks: 5
    21. Memory access:
    22. Via system bus: Yes (8/16/32/64-bit accesses are supported)
    23. Via ProgBuf: Yes (16 ProgBuf entries)
    24. Via abstract command (AAM): May be tried as last resort
    25. DataBuf: 2 entries
    26. autoexec[0] implemented: Yes
    27. Detected: RV64 core
    28. Temp. halting CPU for for feature detection...
    29. HW instruction/data BPs: 8
    30. Support set/clr BPs while running: No
    31. HW data BPs trigger before execution of inst
    32. CSR access via abs. commands: No
    33. Feature detection done. Restarting core...
    34. BG memory access support: Via SBA
    35. SetupTarget() start
    36. ********************************
    37. Pre-selection info
    38. dmcontrol value is: 0x00000001
    39. Current hart id is: 0x00000000
    40. ********************************
    41. ********************************
    42. Post-selection info
    43. dmcontrol value is: 0x00010001
    44. Current hart id is: 0x00000001
    45. ********************************
    46. SetupTarget() end - Took 1.66ms
    47. Memory zones:
    48. Zone: "Default" Description: Default access mode
    49. RISC-V identified.
    50. J-Link>halt
    51. pc = 0000000040004C58 sp = 0000000040047EF0 ra = 0000000040009FBC
    52. gp = 0000000000000000 tp = 0000000040048000 fp = 0000000040047F00
    53. t0 = 0000000000000000 t1 = 0000000000000000 t2 = 0000000000000000
    54. t3 = 0000000000000000 t4 = 0000000000000000 t5 = 0000000000000000 t6 = 0000000000000000
    55. a0 = 0000000000000001 a1 = 0000000000000000 a2 = 0000000000000000 a3 = 0000000000060005
    56. a4 = 0000000000000000 a5 = 0000000000000808 a6 = 0000000000000000 a7 = 0000000000000000
    57. s1 = 0000000040048060 s2 = 0000000000000002 s3 = 0000000000000000 s4 = 0000000000000000
    58. s5 = 0000000040029000 s6 = 0000000040029020 s7 = 0000000000000000 s8 = 000000000000001C
    59. s9 = 0000000040035AB0 s10 = 0000000000000000 s11 = 0000000000000000
    60. J-Link>readcsr 0xF14
    61. CSR 0x0F14: 0x00000000
    62. J-Link>
    Display All
    CSR 0xF14 is "mhartid".

    For reference, here is OpenOCD's output. All is not well here, but it is much better.

    Source Code

    1. Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
    2. Info : J-Link EDU Mini V1 compiled Jun 6 2023 10:50:57
    3. Info : Hardware version: 1.00
    4. Info : VTarget = 3.299 V
    5. Info : clock speed 4000 kHz
    6. Info : JTAG tap: e24.cpu tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
    7. Info : JTAG tap: u74.cpu tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
    8. Info : datacount=2 progbufsize=16
    9. Info : Disabling abstract command reads from CSRs.
    10. Info : Core 0 made part of halt group 1.
    11. Info : Examined RISC-V core; found 5 harts
    12. Info : hart 0: XLEN=64, misa=0x8000000000901107
    13. Info : datacount=2 progbufsize=16
    14. Info : Disabling abstract command reads from CSRs.
    15. Info : Core 1 made part of halt group 1.
    16. Info : Examined RISC-V core; found 5 harts
    17. Info : hart 1: XLEN=64, misa=0x800000000094112f
    18. Info : datacount=2 progbufsize=16
    19. Info : Disabling abstract command reads from CSRs.
    20. Info : Examined RISC-V core; found 5 harts
    21. Info : hart 2: XLEN=64, misa=0x800000000094112f
    22. Info : datacount=2 progbufsize=16
    23. Info : Disabling abstract command reads from CSRs.
    24. Info : Core 3 made part of halt group 1.
    25. Info : Examined RISC-V core; found 5 harts
    26. Info : hart 3: XLEN=64, misa=0x800000000094112f
    27. Info : datacount=2 progbufsize=16
    28. Info : Disabling abstract command reads from CSRs.
    29. Info : Examined RISC-V core; found 5 harts
    30. Info : hart 4: XLEN=64, misa=0x800000000094112f
    31. Info : starting gdb server for u74.cpu0 on 3333
    32. Info : Listening on port 3333 for gdb connections
    33. Info : starting gdb server for u74.cpu2 on 3334
    34. Info : Listening on port 3334 for gdb connections
    35. Info : starting gdb server for u74.cpu4 on 3335
    36. Info : Listening on port 3335 for gdb connections
    37. Info : Listening on port 6666 for tcl connections
    38. Info : Listening on port 4444 for telnet connections
    Display All