In the documentation for emfile it mentions that when using the NAND (micron MT29FWG08A) as the h/w for the file system that the memory controller should be turned off (6.3.2.1) in order to take advantage of the better ECC performance.
Are you just referring to changing the 7 lines used for CE, WE, RE, ALE, CLE, R/B and WP from Alternate Function to one of the GPIO designations for an output? I do see that in coding up the files for driving the NAND that I have to fill in the macro's for driving these lines which is easy enough to do.
Does the memory controller (FSMC on the STM32) still exercise control over the address and data lines if I do this?
There are 2 macro's that appear to be required to change the directionality of the GPIO lines. This means that I'm removing the Data I/O lines from the control of the FSMC and this would be a very bad thing since we have an external SRAM chip. Am I correct in assuming that this will be a major conflict with it's usage?
Cheers!!
Are you just referring to changing the 7 lines used for CE, WE, RE, ALE, CLE, R/B and WP from Alternate Function to one of the GPIO designations for an output? I do see that in coding up the files for driving the NAND that I have to fill in the macro's for driving these lines which is easy enough to do.
Does the memory controller (FSMC on the STM32) still exercise control over the address and data lines if I do this?
There are 2 macro's that appear to be required to change the directionality of the GPIO lines. This means that I'm removing the Data I/O lines from the control of the FSMC and this would be a very bad thing since we have an external SRAM chip. Am I correct in assuming that this will be a major conflict with it's usage?
Cheers!!