[SOLVED] Support for Ibex RV32 core

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  • [SOLVED] Support for Ibex RV32 core

    Hi
    We are trying to use J-Link as a Debug probe for the RISC-V-based 32-bit Ibex core, but are unable to connect it through J-Link. I am attaching a screenshot for better clarity. Can anyone please help us with that?
    We tried device types as RISC-V, RV32, and RV64 but got the error as per snap.
    Thank you.
    Images

    • J-Link_RISCV_Error.jpg

      433.2 kB, 1,388×1,826, viewed 430 times

  • Sounds like your core is in some uncooperative state where it does not respond to debug commands.
    This is usually caused by an application being executed by the core that enters certain low power states or that performs an illegal memory access that never completes and blocks the core + bus.
    I recommend to check for options to inhibit booting of your application code and then check if a debug connection can be established.
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Alex
    Thank you for responding. We don't have any applications running yet. It's just an FPGA with Ibex core-based bitstream on it if that makes sense. We are trying to use J-Link commander for downloading the binary and running the application but this issue doesn't allow us to connect in the first place.

  • Is it possible that you have a setup like this?
    wiki.segger.com/J-Link_RISC-V#RISC-V_behind_a_CoreSight_DAP

    If yes, you need to tell J-Link, where in the CoreSight address space it finds the core, as there is no auto-detection like for Cortex-M / Cortex-A cores.
    See wiki article for more information and examples.


    BR
    Alex
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Alex
    Yes, our setup is something like this. We are having two cores: RV32 and Cortex-M33 hooked through the JTAG chain. We did change the Core base address for RV32 but still seeing the same error. Is it possible to get an example J-Link script for this configuration?

    We are using below J-Link script:

    int InitTarget(void) {
    JLINK_SYS_Report("*******J-Link Script Running******");
    JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0xA");
    JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 0x0");
    return 0;
    }

    Thank you!

    Regards
    SJ

  • Hi,

    Actually, there is an example in the wiki, that shows you what variables to set.
    To which values they need to be set, depends on your setup and you know that better as we do.
    Unfortunately, I cannot share any real-world examples with you because all scripts we did so far for such setups are for customer SoCs which are under NDA.
    What I can tell you is that 0xA for the "core base address" sounds odd. It has to be some 4 KB aligned address.

    If you are interested in having us writing such a script for you as a service, feel free to request it:
    segger.com/support/technical-support/
    (Select general query and refer to this thread)

    Requirements would be:
    1. Getting us physical access to hardware or at least access to it, via J-Link Remote Server in tunnel mode. (segger.com/products/debug-prob…te-server/#in-tunnel-mode)

    2. Providing all debug related information to us (how your CoreSight memory map looks like, etc.)



    BR
    Alex
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi
    I have to check whether we can provide physical access or not. But I was wondering if you can briefly explain how does J-Link reads the DMI register.
    I understand that for ARM it looks into ROM tables but since these tables are not applicable for RISCV, how do they read the DMI register for RISCV?
    Is the register address need to be memory mapped in Coresight address space or just providing the absolute address of these registers on RISCV would work?
    When J-Link identified the core behind the DAP, what is the next thing it does before requesting a halt to the core?

    Thank you!

  • Sorry for the delay.
    It looks like we have misread your setup.
    We guessed that your ARM core + RISC-V core are both accessible through the DAP TAP (IRLen = 4).
    But it seems that in your case there are 2 TAPs:
    1 for the DAP TAP to access the ARM core
    1 for the RISC-V TAP
    If this is the case then yes, indeed you need to provide a known IDCODE for that RISC-V TAP to J-Link.

    Good to hear that you are up and running.
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.