[SOLVED] Segger Jlink and i.mx8 binary upload - dazed and confused

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  • [SOLVED] Segger Jlink and i.mx8 binary upload - dazed and confused

    I currently use IAR workbench and a Segger JLINK ULTRA+ to run simple test routines on the m4 side of the i.mx8 processor. This works.

    I am now attempting to use JLINK commander to do the same, but have running into difficulties. The same code compilation is being used for the IAR build, however, IAR uses a *.out file whereas the Jlink only accepts the *.bin version of the compiled file. The IAR workbench is setup to generate both file types.

    So far I am able to use JLINK to connect to the device, write the binary file to RAM and verify the binary is stored in the correct location. When I attempt to run the program , however, it appears to not execute properly.

    Here is the commander script that I have been using:

    device MIMX8MM3_M4
    speed 4000
    si jtag
    rsettype 0
    h
    setpc 1ffe0000
    loadfile c:/mc_code/raw_test_code.bin 1FFE0000
    verifybin c:/mc_code/raw_test_code.bin 1FFE0000
    r

    At this point, if I type "go" at the command prompt, I should see a message from my program out the com port, but instead see nothing. If I halt the program, the program counter stops at memory address 1FFE4786.

    If I rerun the script, and then step through the code line by line, I get a "T-BIT of XPSR is 0 but should be 1. Changed to 1" response. The screen capture attached is of what I observe when I start stepping through the code.

    After this point, the program counter seems to go to address 0x000000 which is outside the range of RAM addressing. Shortly after that, it winds up at 1FFE4786.

    So I am now pulling my hair out as to why it is doing this.

    Please help to straighten this out for me if you can.
    Images
    • Capture - step through program.JPG

      52.8 kB, 578×494, viewed 195 times
  • Besides setting the PC, did you also make sure that you set xPSR and SP (R13) accordingly?
    Most startup codes etc. expect the core to be in reset state, so SP is setup automatically for Cortex-M by the core on reset (by loading the SP address from VTOR + 0x0).
    Also xPSR has a defined reset, and so the SP selection does (MSP / PSP selected as active SP)

    Maybe one of these steps is missing in your case when doing things from J-Link Commander instead of the IDE.
    You can check what IAR is doing on debug session start, by activating the J-Link log file:
    wiki.segger.com/Enable_J-Link_log_file


    BR
    Alex
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

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  • The following script seems to work ok:

    device MIMX8MM3_M4
    speed 1000
    si jtag
    jtagconf -1 -1

    setreset
    sleep 200
    rsettype 0
    r

    setpc 1ffe0000
    wreg "R15 (PC)", 1FFE53B0
    wreg "XPSR", 01000000

    loadfile c:/mc_code/raw_test_code.bin 1FFE0000
    verifybin c:/mc_code/raw_test_code.bin 1FFE0000

    g