Hello
Segger Embedded Studio for RISC-V helps me to debug a RISC-V processor. The debugging works great. Unfortunately, I have now run into a problem that I don't know how to solve.
I have built a buffer memory that is filled by UART. As soon as this is full, an interrupt signal is generated and jumped into trap_entry. From this trap_entry follows the jump into handel_trap. The handel_trap always jumps back to itself with the command J. Unfortunately, I don't know how to change the command to handel_trap.
I hope you can help me.
I have attached a photo showing the program code and the assembler code in trap_entry and handel_trap. In addition, the program main.c contains some examples of how I thought to change the content of handel_trap but non works.
Segger Embedded Studio for RISC-V helps me to debug a RISC-V processor. The debugging works great. Unfortunately, I have now run into a problem that I don't know how to solve.
I have built a buffer memory that is filled by UART. As soon as this is full, an interrupt signal is generated and jumped into trap_entry. From this trap_entry follows the jump into handel_trap. The handel_trap always jumps back to itself with the command J. Unfortunately, I don't know how to change the command to handel_trap.
I hope you can help me.
I have attached a photo showing the program code and the assembler code in trap_entry and handel_trap. In addition, the program main.c contains some examples of how I thought to change the content of handel_trap but non works.