[SOLVED] Could not access to the my own RISC-V core via cJtag protocal

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  • [SOLVED] Could not access to the my own RISC-V core via cJtag protocal

    Hi segger experts,

    Recently, I've met the following case and i've no idea to fix that, could you please help check that?

    Issue:
    If I choose the official RV32 as the device for my risc-v platform, then it can be accessed via Jlink-cJTAG; but if I define my own device name in the JLinkDevices.xml file, it cannot be accessed.

    Steps:
    1. Select the official RV32 as the device.

    2. You could see my risc-v platform can be accessed via cJTAG.3. Now I add my own device into the JlinkDevices.xml, meanwhile named the Vendor is "VendorTest" and the device name is "TestDevice" just as the following shows:


    4. Select the TestDevice.


    5. My risc-v platform can not be accessed!
    I need to add my own device name into the JlinkDevice.xml so that I can use my flashloader, but now it sees there exists problem to access the risc-v core via cJTAG in such way :( .

    Have you met such issue before and how to fix that?

    Thanks in advance,

    Gavin

    Best Regards,
  • Supplementary Instructions:

    Hi segger experts,
    I notice that the jlink cJtag accesses to core successfully, the ConfigTargetSettings() would be done before access core, but if choose my device from JlinkDevcices.xml, there has no such operation and the jlink cJtag can't access to the acore. Maybe that is reason. So could you point out what does the ConfigTargetSettings() do to risc-v core?



    Thanks a lot,

    Gavin
  • Hi Gavin,
    is there a specific reason why you are adding a new device instead of extending the existing RV32?
    It should work when extending the RV32, as it will use the same connection sequence and simply add the specified flash range.
    wiki.segger.com/Open_Flashload…ending_an_Existing_Device

    If you need to add a new device:
    The RV32 requires the short cJTAG init sequence.
    J-Link uses the long one by default, because it is the one used by most RISC-V architectures.
    For more information and how to adjust this, please see the following article:
    wiki.segger.com/J-Link_cJTAG_s…cs#Short_connect_sequence

    Best regards,
    Fabian
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Just to be precise / correct on Fabian‘s latest statement:
    Most RISC-V cores implement the short connect sequence. The short sequence is NOT standard compliant.

    The long sequence is standard compliant. Therefore, the long one is used by default, if not specified otherwise.

    However, the links Fabian provided are fine and will get you to your goal.
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.