Hi,
I'm using a Jlink Ultra on a Cortex-M4 based ATSAMg55J19. The JLink DLL is 7.60c
The default reset strategy sometimes fails to gain control of the processor after reset. I can mitigate this by using RX 100 from JlinkExe.
However, I'd like to pull Reset# low to get (hopefully) better results and also to reset other devices in the system which are also wired to Reset#. See below.
A second question is how to make Ozone set the reset type and reset delay.
Thanks,
Dale
[edt@sleet JLink]$JLinkExe
SEGGER J-Link Commander V7.60c (Compiled Jan 7 2022 16:13:49)
DLL version V7.60c, compiled Jan 7 2022 16:13:33
Device "ATSAMG55J19A" selected.
Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[0][1]: E0001000 CID B105E00D PID 003BB002 DWT
[0][2]: E0002000 CID B105E00D PID 002BB003 FPB
[0][3]: E0000000 CID B105E00D PID 003BB001 ITM
[0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
Cortex-M4 identified.
J-Link>rst 2
Reset type RESETPIN: Resets core & peripherals using RESET pin.
J-Link>reset
Reset delay: 0 ms
Reset type RESETPIN: Resets core & peripherals using RESET pin. <----------------- Does NOT Pull Reset# low,
J-Link>ishalted
CPU is halted (PC = 0x00404848).
J-Link>r0 <------------------------------------------------------------------------------- Does Pull Reset# low
J-Link>r1 <--- Reset# back high
J-Link>
I'm using a Jlink Ultra on a Cortex-M4 based ATSAMg55J19. The JLink DLL is 7.60c
The default reset strategy sometimes fails to gain control of the processor after reset. I can mitigate this by using RX 100 from JlinkExe.
However, I'd like to pull Reset# low to get (hopefully) better results and also to reset other devices in the system which are also wired to Reset#. See below.
A second question is how to make Ozone set the reset type and reset delay.
Thanks,
Dale
[edt@sleet JLink]$JLinkExe
SEGGER J-Link Commander V7.60c (Compiled Jan 7 2022 16:13:49)
DLL version V7.60c, compiled Jan 7 2022 16:13:33
Device "ATSAMG55J19A" selected.
Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[0][1]: E0001000 CID B105E00D PID 003BB002 DWT
[0][2]: E0002000 CID B105E00D PID 002BB003 FPB
[0][3]: E0000000 CID B105E00D PID 003BB001 ITM
[0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
Cortex-M4 identified.
J-Link>rst 2
Reset type RESETPIN: Resets core & peripherals using RESET pin.
J-Link>reset
Reset delay: 0 ms
Reset type RESETPIN: Resets core & peripherals using RESET pin. <----------------- Does NOT Pull Reset# low,
J-Link>ishalted
CPU is halted (PC = 0x00404848).
J-Link>r0 <------------------------------------------------------------------------------- Does Pull Reset# low
J-Link>r1 <--- Reset# back high
J-Link>