[SOLVED] SWD fails when Logic Analyzer is (directly) attached

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  • [SOLVED] SWD fails when Logic Analyzer is (directly) attached

    Hello together,

    I am having a problem tracing a SWD connection, because as soon as the clock signal line is connected to the Logic Analyzer (ADALM2000), my Segger J-Link EDU refuses to work.

    DUT is a custom PCB with Dialog DA14695 MCU. Schematics and PCB-Layout was done by someone else (semi-professional).

    There are no external pull up / down for the SWD lines since the DA14695 integrates internal ones. Their reset states are: pull-up for SWDIO and pull-down for SWCLK - according to the specs.

    My setup is as follows:
    - J-Link EDU SWD connected to the DUT via a breadboard (GND, VCCref=3V, SWDIO and SWDCLK).
    - ADALM2000 Digital Inputs connected to the breadboard (GND, D0 = SWCLK, D1 = SWDIO)

    When I try to connect to the DUT via SWD, the J-Link EDU LED flashes RED a few times, meaning it resets (as far as I know). However, when I disconnect D0 (SWDCLK) at the Logic Analyzer, it works perfectly.

    Interestingly, everything is fine when I connect a 1k resistor in series. I can connect to the DUT via SWD and trace the SWD signal with the Logic Analyzer.

    The Logic Analyzer operates at nominal 3.3V LVCMOS and the Segger operates at VCCref (currently ~ 3V).

    I am working here with an HP EliteBook laptop and tried already with detached power supply but either no success without series resistor.

    At first I powered the DUT with a stabilized lab power supply and shared GND with the J-Link and the Logic Analyzer.

    There is nothing (relevant) floating.
    I even powered the DUT completely via it's USB-C port (the board features an USB charging detection circuit and the DA14695 is able to run from VBUS, providing all necessary power-lines via its integrated PMU).

    Unfortunately, even when the board is completely powered via the laptop and is completely separated from any other external power source, the issue still exists.

    I would like to understand why it does not work when there is no series resistor in between. Clock line current consumption is about 1.3 uA (on average, since clock signal and measured with simple multimeter) at 1 kHz without series resistor and a tiny bit less with .

    I already though of an increased capacitance on the line. But currently I am not able to capture some scope traces.

    Kind regards
  • Hi,
    This does not sound like a J-Link related issue, but a board design question.
    It looks like something is disturbing the signals.

    I would suggest to
    - check the signal integrity,
    - compare the board design with the specifications for SWD and
    - compare the board design with a related evaluation board.

    We will will close this thread now.

    Best regards,
    Fabian
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