[SOLVED] ATSAME51N19 SWO not working properly

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  • [SOLVED] ATSAME51N19 SWO not working properly

    Hi all,

    I'm trying to get a decent SWO output from the ATSAME51N19A mcu I'm working with.
    So far it's not working like it should.

    I'm working with Microchip Studio V7.0.2542, CMSIS V5.4.0 and DFP 1.1.129 and 1.1.139
    My debugger is a J-LINK Plus with a 6-pin Tag Connect
    I've attached my current code.

    I'm not getting any SWO data in both Microchip Studio and Ozone.
    It partially works with J-Link SWO Viewer V6.98, but not in the way I'm expecting.

    If I boot the SAME, open SWO Viewer, select ATSAME51N19 (Automatically sees 120MHz clkspeed) and press OK I can see the stream of B's that are in the while(1).
    But if I then reboot the MCU I don't get any data at all. I have to go to edit -> Configure -> ok, and after that I get my stream of B's again.
    I never see the A.

    I've also tried Ozone V3.22.
    Select device and SVD file, select Jlink, open .ELF and set trace to SWO with auto frequency for MCU and SWO
    I can see the sourcecode, I can program and debug everything, but I don't get any SWO output, ever.

    What can I do to fix this?

    C Source Code

    1. #define CM4_TRACE_GCLK_ID 47
    3. #define CPU_FREQUENCY 120000000UL
    4. #define SWO_PRINT_PORT 0
    5. #define SWO_FREQUENCY 6000000UL
    6. #define SWOPRESCALE (((CPU_FREQUENCY)/(SWO_FREQUENCY)) - 1)
    7. #define ITM_ID ((1UL << ITM_TCR_TraceBusID_Pos) & ITM_TCR_TraceBusID_Msk)
    9. void Initialize_SWO(void)
    10. {
    11. CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // enable access to the trace component registers.
    13. TPI->SPPR = 0x2UL; // Selected Pin Protocol Register -> Serial Wire Viewer, UART NRZ
    14. TPI->ACPR = SWOPRESCALE;
    15. ITM->LAR = 0xC5ACCE55UL; // unlock the ITM
    16. ITM->TCR = ITM_TCR_ITMENA_Msk | ITM_TCR_TSENA_Msk | (1UL << ITM_TCR_TraceBusID_Pos) | ITM_TCR_DWTENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_SWOENA_Msk; // Enable ITM
    17. ITM->TER = 0xFFFFFFFF; // ITM Trace Enable Register
    18. ITM->TPR = 0;
    19. };
    21. int main(void)
    22. {
    23. REG_NVMCTRL_CTRLA |= NVMCTRL_CTRLA_RWS(6); //Set flash waitstates to 6
    24. REG_NVMCTRL_CTRLA &= ~NVMCTRL_CTRLA_AUTOWS; //Disable auto waitstates
    25. PORT->Group[1].DIRSET.reg |= PORT_PB30;
    26. PORT->Group[1].PINCFG[30].reg |= PORT_PINCFG_PMUXEN;
    27. PORT->Group[1].PMUX[30/2].reg |= PORT_PMUX_PMUXE(0x07); //Set PB30 to CORTEX_CM4/SWO mux H
    29. XOSC32K_Initialize(); //Init external 32khz crystal
    30. FDPLL0_Initialize_120MHz(); //Set FDPLL0 to 120MHz and MCLK to DIV 0x01
    31. GCLKn_Initialize(GCLK_ID_0, GCLK_SRC_FDPLL0, 1); //Connect GCLK0 and MCLK to FDPLL0 at 120MHz
    32. REG_GCLK_PCHCTRL47 = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(0x00); //Connect GCLK0 to CM4_TRACE_GCLK_ID
    33. while(!(REG_GCLK_PCHCTRL47 & GCLK_PCHCTRL_CHEN)) {__ASM("nop");} //Wait for synchronization
    35. Initialize_Systick(Systick_OVERFLOW_1000Hz); //1ms systick interrupt for Delay() function
    36. Initialize_SWO();
    38. Delay(500); //500ms delay
    40. ITM_SendChar('A');
    42. while(1)
    43. {
    44. Delay(100);
    45. ITM_SendChar('B');
    46. }
    47. }
    Display All

  • Hello,

    Thank you for your inquiry.
    If I had to guess the reason for SWO not working reliably is an incorrect initialization as on most higher speed ATSAM devices the SWO pin does not follow the CPU clock speed 1/1:
    wiki.segger.com/ATSAME70

    This can be mitigated with a JLinkScript and functions SWO_GetSWOBaseClock and SWO_EnableTarget.

    We will add this device to our Todo to add native support to our J-Link software. But as our resources are quite booked right now we can't name a fixed time schedule.

    Alternatively you can add support yourself via the JLinkScript. Documentation can be found here:

    wiki.segger.com/J-Link_script_files


    Best regards,

    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Nino,

    Thanks for your response.
    If I understand correctly the ATSAME51 isn't fully supported yet?

    I understand that it's hard to name a fixed time schedule.
    But do you have any idea how long it could take? (Days,weeks,months?)

    We are currently actively developing for the ATSAME51 and we've bought two J-Link Plus devices for programming/debugging and we hoped to use the SWO lines.

    I will look into the jlink script, but I'm new to Jlink so that can take a while.
    The core starts with 48MHz clock and we switch it to 120MHz clock on startup.
    Does this matter for a jlink script?
    (I'd like to be able to post SWO information on startup, before and after the 120MHz switch)

    Do you already have a working script for the ATSAME70?
    Is it possible for me to take a look in this script and edit it for the ATSAME51?

    Kind regards,
    Martijn

  • Hi Martijn,

    Marty-VB wrote:

    If I understand correctly the ATSAME51 isn't fully supported yet?
    It is fully supported from J-link perspective. However for SWO this particular target device can have a multitude of clocksources, sometimes different pins can be used etc.
    It is impossible to us to guess all possible setups. Arm default is SWO speed follows CPU clock speed and only 1 SWO pin is available.
    Everything else is special handling and it is user responsibility to set it up.

    Nonetheless we will create one native init for the SAMD54 XPlained Pro board which will work out of the box.
    But only if you use the same board and same clock source. Other setups might not be covered. That is why we provide the JLinkScript interface so you can adjust the settings to fit your needs.
    A rough estimate for our implementation is 3-4 weeks due to the currently booked situation of our resources.

    Marty-VB wrote:

    The core starts with 48MHz clock and we switch it to 120MHz clock on startup.
    Does this matter for a jlink script?
    It only matters what clock the SWO module is clocked with. On this device it is most likely independent of the CPU core clock. So set it to whatever you use as the SWO base clock and you should be good to go.


    Marty-VB wrote:

    Do you already have a working script for the ATSAME70?
    Is it possible for me to take a look in this script and edit it for the ATSAME51?
    Yes we have a working script for the SAME70 as described in the Wiki.
    If you like we an provide it to you as reference so you can create your own easier for SAME51.

    Simply open a ticket as described in my signature in the J-Link group and reference this thread. We will provide you with the script source then.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.