[SOLVED] CPU could not be halted - Cortex-M33 (SEGGER J-Link EDU V10.10)

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  • [SOLVED] CPU could not be halted - Cortex-M33 (SEGGER J-Link EDU V10.10)

    Hello,

    I am using a NXP board containing a Cortex-M33 but i am not able to erase, reset or program the board.
    when trying to connect i get the following:

    J-Link>connect
    Device "CORTEX-M33" selected.

    Connecting to target via SWD
    Found SW-DP with ID 0x6BA02477
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    FPUnit: 8 code (BP) slots and 0 literal slots
    Security extension: implemented
    Secure debug: disabled
    CoreSight components:
    ROMTbl[0] @ E00C0000
    ROMTbl[0][5]: C0181000, CID: 00000000, PID: 00000000 ???
    ROMTbl[0][6]: C0182000, CID: 00000000, PID: 00000000 ???
    ROMTbl[0][7]: C0183000, CID: 00000000, PID: 00000000 ???
    ROMTbl[0][8]: C0184000, CID: 00000000, PID: 00000000 ???
    ROMTbl[0][9]: C0185000, CID: 00000000, PID: 00000000 ???
    ROMTbl[0][10]: C01BF000, CID: 00000000, PID: 00000000 ???
    Cortex-M33 identified.

    When I try to reset:

    J-Link>r
    Reset delay: 0 ms
    Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: CPU did not halt after reset.
    Reset: Using fallback: Reset pin.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x6BA02477
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    CPU could not be halted
    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x6BA02477
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    CPU could not be halted
    Reset: Failed. Toggling reset pin and trying reset strategy again.
    Found SW-DP with ID 0x6BA02477
    SWD speed too high. Reduced from 4000 kHz to 2700 kHz for stability
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via AIRCR.SYSRESETREQ.
    Reset: CPU did not halt after reset.
    Reset: Using fallback: Reset pin.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x6BA02477
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    CPU could not be halted
    Reset: Core did not halt after reset, trying to disable WDT.
    Reset: Halt core after reset via DEMCR.VC_CORERESET.
    Reset: Reset device via reset pin
    Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    Reset: Reconnecting and manually halting CPU.
    Found SW-DP with ID 0x6BA02477
    DPIDR: 0x6BA02477
    AP map detection skipped. Manually configured AP map found.
    AP[0]: AHB-AP (IDR: Not set)
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00C0000
    CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
    Found Cortex-M33 r0p4, Little endian.
    CPU could not be halted
    CPU could not be halted

    ****** Error: Failed to halt CPU.

    What could be causing this behaviour? Any help would be appreciated.

  • Almost all NXP devices nowadays need special connect and reset sequences.
    For this, J-Link needs to know the exact device.
    You selected generic “Cortex-M33” which is most probably not sufficient here.

    Flash programming / erasing of course will also not work with this setting, as every flash controller is different and needs a matching algorithm that makes use of it.

    For a list of supported device names:
    segger.com/downloads/supported-devices.php


    BR
    Alex
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