Hello,
Is it possible to use Embedded Studio, and more specifically the Segger linker, to develop applications on STM32H7 dual-core processors?

How do we inform the linker, when we compile for a core (in a project), of the space taken in the different sections by the other core (in another project, but in the same solution)?

In the project window, which organization should we choose to organize a double core project as best as possible?

Best regards,
Jean-Louis

Hello Nino,

"Just make sure they do not overlap" Of course ! But normally, it is precisely the role of the linker to deal with overlapping variables.

And how do we do for common variables?
Should each of us set its address so that they can be seen by the respective projects?

On a big project, I fear that it represents a lot of work and is the source of many errors.

Best regards
Jean-Louis

What I expected is that there is a master project corresponding to a given core, and that the place of variables and functions of each additional core is allocated sequentially by the linker. Obviously, variables (and functions?) With the same name would be common ...Is this an unattainable dream?

ps thanks for the links

Hello,
thank you for your reply

Unfortunately, to say the least, the development of multi-core applications is not well documented.

Among manufacturers, there is a lot, a lot, more money spent on marketing to promote the products than on documentation explaining how to use them.

The few rare documents that we find focus on the multi-core debug, which is (perhaps) an important point, although I strongly doubt its real interest (to begin with, it would be good if the IDE did not crash not when I pass a single debugger from one heart to another - which is the case, for me, on IAR- before talking about simultaneous multi-core debug).
st.com/content/ccc/resource/te…lations/en.DM00629855.pdf
freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html#DemoApp
static.linaro.org/connect/san19/presentations/san19-102.pdf
But these documents do not speak of what is happening at the linker level, which is however the heart of the problem.

At Segger, you are fortunate to have mastery of the whole chain, and therefore the opportunity to do something that is a little less archaic than what is offered in others ... It seems, the reason you had developed your own linker, right?
Basically, it doesn't seem very complicated (for basic functionality):
- define a hierarchy in the order in which the variables associated with the core are organized in the different memories (this amounts to saying, when linking the core "n", to start arranging the variables from the location defined by the last address allocated for the core “n-1”
- define some pragma to tell the linker if the variables (and/or functions) are common or not to different cores.

But ... I understand that this is not a priority ... I will try to do with what I have ...
Is it possible, in the IDE, in the options associated with the linker, to define an offset which would make it possible to shift the allocation of variables by a certain value in a given section (so as not to have to modify the MemoryMap.xml files)?

Best regards
Jean-Louis