Hello,

by observing how J-Link Commander (JLinkExe) behaves, I understand that "rreg" and "wreg" commands do not read and write to/from processor registers immediately but instead work with cached values. New values are written to the CPU registers only when the processor is resumed. Is my observation correct?

An example of that situation when working with my RISC-V target:

J-Link>ishalted
CPU is halted.
J-Link>wreg tselect 1
TSELECT = 0x00000001
J-Link>rreg 1952
TSELECT = 0x00000001 <---- TSELECT is not yet written to CPU
J-Link>rreg 1953
TDATA1 = 0x28001044 <---- Makes impression that TDATA1 for trigger #1 equals this value, which is not true.
J-Link>wreg tselect 2
TSELECT = 0x00000002 <---- The same situation for trigger #2
J-Link>rreg 1952
TSELECT = 0x00000002
J-Link>rreg 1953
TDATA1 = 0x28001044

The caching behavior may be misleading for the user (as apparent from the example above) and also prevents the user from doing certain operations with the RISC-V core, for example:

• The trigger inspection or enumeration (e.g. the trigger enumeration algorithm from RISC-V spec 0.13, chapter 5
  
• Inspection of any register that has the write-any-read-legal semantics - you can't really check the real value of the register, because:
  
  • prior to resuming the core, you only read the cached value (exactly equal to what you wanted to write)
    
  • after resuming the core, the register value may already be clobbered by the program or by the core itself
    
  ... perhaps there are more limitations which I will yet encounter
  

Is there any mechanism how to suppress the caching and make J-Link Commander do the register reads and writes immediately, without caching it and waiting for processor resume?

For example OpenOCD has "force" option for "reg" command, which suppresses any caching when reading registers: openocd.org/doc/html/General-Commands.html#index-reg

If such feature is not available, would it be possible to implement it?

Thank you, regards
Jan