With regards to my previous thread on the Segger Forum:
[SOLVED] Locking and Unlocking JTAG port on TI RM48 AJSM using J-link Base

We need to write a Jlinkscript file that would perform unlocking of the TI JTAG port via the AJSM tap. The procedure to do this is not well documented, but i guess with some experiments could be achieved. I assume i will need to perform my unlocking of the CPU in the InitTarget() function, as the Locking will only leave the ICEPick and AJSM Taps open for use.

There are however not any examples for this processor using the TI ICEPick module. Especially the procedure to actually initialize the target (InitTarget).

When running a debug session from IAR, i see the following output just before the debugging session starts:

Tue Apr 16, 2019 09:51:11: Device "RM48L5X" selected.

Tue Apr 16, 2019 09:51:11: JTAG speed is initially set to: 12000 kHz
Tue Apr 16, 2019 09:51:11: Executing InitTarget()
Tue Apr 16, 2019 09:51:11: TotalIRLen = 6, IRPrint = 0x01
Tue Apr 16, 2019 09:51:11: J-Link script: ICEPick found, enabling Cortex-M3 core.
Tue Apr 16, 2019 09:51:11: TotalIRLen = 10, IRPrint = 0x0011
Tue Apr 16, 2019 09:51:11: JTAG chain detection found 2 devices:
Tue Apr 16, 2019 09:51:11: #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Apr 16, 2019 09:51:11: #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
Tue Apr 16, 2019 09:51:11: ARM AP[0]: 0x44770001, AHB-AP
Tue Apr 16, 2019 09:51:11: ARM AP[1]: 0x24770002, APB-AP
Tue Apr 16, 2019 09:51:11: ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-007BBC14 Cortex-R4
Tue Apr 16, 2019 09:51:11: Found Cortex-R4 r1p3
Tue Apr 16, 2019 09:51:11: 6 code breakpoints, 2 data breakpoints
Tue Apr 16, 2019 09:51:11: Debug architecture ARMv7.0
Tue Apr 16, 2019 09:51:11: Data endian: little
Tue Apr 16, 2019 09:51:11: Main ID register: 0x411FC143
Tue Apr 16, 2019 09:51:11: TCM Type register: 0x00010001
Tue Apr 16, 2019 09:51:11: MPU Type register: 0x00000C00
Tue Apr 16, 2019 09:51:11: System control register:
Tue Apr 16, 2019 09:51:11: Instruction endian: little
Tue Apr 16, 2019 09:51:11: Level-1 instruction cache disabled
Tue Apr 16, 2019 09:51:11: Level-1 data cache disabled
Tue Apr 16, 2019 09:51:11: MPU enabled
Tue Apr 16, 2019 09:51:11: Branch prediction enabled
Tue Apr 16, 2019 09:51:11: Executing ResetTarget()
Tue Apr 16, 2019 09:51:11: Executing SetupTarget()
Tue Apr 16, 2019 09:51:11: TMS570LS: HandleSetup(): Initializing ECC protected RAM
Tue Apr 16, 2019 09:51:11: Hardware reset with strategy 1 was performed
Tue Apr 16, 2019 09:51:11: Initial reset was performed
Tue Apr 16, 2019 09:51:11: Found 2 JTAG devices, Total IRLen = 10:
Tue Apr 16, 2019 09:51:11: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Apr 16, 2019 09:51:11: #1 Id: 0x4B8A002F, IRLen: 6, IRPrint: 0x1 TI ICEPick
Tue Apr 16, 2019 09:51:11: execUserFlashInit
Tue Apr 16, 2019 09:51:11: Executing SetupTarget()
Tue Apr 16, 2019 09:51:11: TMS570LS: HandleSetup(): Initializing ECC protected RAM
Tue Apr 16, 2019 09:51:11: Hardware reset with strategy 0 was performed
Tue Apr 16, 2019 09:51:11: Executing memory setup macro RM4x Flash
Tue Apr 16, 2019 09:51:12: 3900 bytes downloaded (17.39 Kbytes/sec)
Tue Apr 16, 2019 09:51:12: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\TexasInstruments\FlashRM48L950.out
Tue Apr 16, 2019 09:51:12: Target reset
Tue Apr 16, 2019 09:52:00: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\TexasInstruments\FlashRM4x.mac
Tue Apr 16, 2019 09:52:00: Downloaded ..\TII-SRV.out to flash memory.
Tue Apr 16, 2019 09:52:00: Executing SetupTarget()
Tue Apr 16, 2019 09:52:00: TMS570LS: HandleSetup(): Initializing ECC protected RAM
Tue Apr 16, 2019 09:52:00: Hardware reset with strategy 1 was performed
Tue Apr 16, 2019 09:52:04: 2097152 bytes downloaded into FLASH (39.00 Kbytes/sec)
Tue Apr 16, 2019 09:52:04: Loaded debugee: ..\TII-SRV\Output\Debug\Exe\TII-SRV.out
Tue Apr 16, 2019 09:52:04: Software reset was performed
Tue Apr 16, 2019 09:52:04: Target reset


I see that the InitTarget() function must at least call some sort of JlinkScript to setup the JTAG via the ICEPick.

The JLink documentation UM08001 says the following about TI ICEPick :
- p116 some devices need special connect sequences (e.g. devices with TI ICEPick modules)
- p170 Example devices are MCUs from TI which have a so-called ICEPick JTAG unit on them that needs to be configured via JTAG, before the actual CPU core is accessible via JTAG.

Is there anywhere i can find an example of the sequence required in my InitTarget() procedure to mimic the one supplied by Segger in the DLL?

Regards,
Chris