Hello,
I believe the TMS570LCxx and RM57LCxx Texas Instruments chips (cortex-r5) that SEGGER supports only support the 4MB internal flash region mapped from 0x0 - 0x400000. However, the two chips both have another 128KB of "Emulated EEPROM", which is programmable via the same TI library, memory-mapped at 0xF0200000. However, this flash has some differences with regards to the flash controller in terms of how to program the section. It seems like today, this EEPROM (which is just flash under the hood) is not supported by SEGGER tools. A use-case example would be when I try to run the 'load' command using gdb (connected to JLinkGDBServer) on an ELF file containing loadable sections in the 0xF0200000+ region, those sections would get flashed to EEPROM. Instead, the EEPROM always appears to be untouched.
If I'm wrong, and the 128KB EEProm section is already supported by SEGGER tools, I was wondering if anyone could point me in the direction of some documentation that would help solve this problem or should it "just work" given an .srec or .elf file with sections placed at those addresses?
I believe the TMS570LCxx and RM57LCxx Texas Instruments chips (cortex-r5) that SEGGER supports only support the 4MB internal flash region mapped from 0x0 - 0x400000. However, the two chips both have another 128KB of "Emulated EEPROM", which is programmable via the same TI library, memory-mapped at 0xF0200000. However, this flash has some differences with regards to the flash controller in terms of how to program the section. It seems like today, this EEPROM (which is just flash under the hood) is not supported by SEGGER tools. A use-case example would be when I try to run the 'load' command using gdb (connected to JLinkGDBServer) on an ELF file containing loadable sections in the 0xF0200000+ region, those sections would get flashed to EEPROM. Instead, the EEPROM always appears to be untouched.
If I'm wrong, and the 128KB EEProm section is already supported by SEGGER tools, I was wondering if anyone could point me in the direction of some documentation that would help solve this problem or should it "just work" given an .srec or .elf file with sections placed at those addresses?