We are attempting to trace a custom board with a Zynq 7020device using JTrace Pro and Ozone. We have enabled the ETM using 4 trace datapins at 75MHz (trace clock) from the ARM core(s) in the Zynq device. We haveconnected the 4 trace data lines, trace clock and JTAG as described in (many)app notes. The trace signals go through the FPGA fabric and use the EMIO. Ozoneis able to connect to the device, halt it, restart it, display memory, step instructionsbut no trace data is produced.

When the application if running under Ozone, the traceindicator LED is red. When the application is halted, the trace indicator LEDis green. I have tried using JTrace through USB and Ethernet and the behavior isthe same.

The webserver trace status indicates:
Trace clock: 74990kHz
Half-syncdetection: 0xFFF7FFFF (Not O.K. nohalf-sync pattern detected)
Last incorrect half-syncsampled: 0xFFF7FFFF
Changing the delay has no beneficial effect. The trace clockswitches between 75000 kHz and 74990 kHz
The half sync detection occasionally changes to 0xF7F7FFFFor 0xFF7FFFFF if I adjust the timing while the application is running. If theapplication is not running the value never changes.

We are kind of at our wit’s end here and would appreciatesome direction to get trace working? Am I forgetting something in the Ozonesetup? Could it be a Zynq setup issue?

Running the tutorial and the trace demo board works just fine.

We are using the very latest Ozone, JLink and JTrace firmware.

Any thoughts would be appreciated

Hi Nino,

Thanks for your response. The zc702 board (xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) has a 7020 on it and with the purchase of the XM105 FMC card (xilinx.com/support/documentation/boards_and_kits/ug537.pdf) it is possible to route the trace pins out through the EMIO to the FMC card pins and connect a trace cable (xilinx.com/support/answers/46915.html). Our custom board is similar to that. We use 4 EMIO pins as our trace pins and route the trace clock through the fabric to the IO as well. This functionality should in no way effect the trace set up. The only potential complexity I see is setting up the "funnel" connection properly to collect trace information from either or both ARM cores.

While providing an actual init sequence may be difficult or beyond the call of duty for you or your team, a few hints and pointers - specifically related to setting up the funnel - would be helpful.

The initialization is part of the device boot up sequence. It is incorporated in the ps7_init file and loaded as part of the boot sequence that is generated by Xilinx design tools