[SOLVED] J-Trace Pro Performance on High-Speed ARM Cores

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  • [SOLVED] J-Trace Pro Performance on High-Speed ARM Cores

    I believe the J-Trace Pro operates 4 lanes at 150 MHz but that it is double data-rate so 4 at 300 MHz. What are the limitations of this device when used with a core running at 600 MHz or above? For example the i.MX RT1050 Cortex-M7 devices from NXP has a maximum clock speed of 600 MHz and some Cortex-A devices clock at over 1 GHz.

  • Hello,

    Thank you for your inquiry.
    Your questions should be answered by our blog post to this topic: blog.segger.com/current-state-of-the-trace-market/
    It basically boils down to a trade off the silicon vendors have to make. Either fast GPIOs that can keep up with 1 GHz devices at 4-bit trace (very expensive in silicon, no trace debug probe available at that speeds), wider trace port width (barely supported, many pins (up to 32) lost for a debug feature), or the so far most popular option, limit the maximum trace clock at ~100 Mhz no matter how fast the CPU is and hope the customers do not use complex applications that might overflow the buffers.

    Should we see more chips using option 1 and 2 instead of 3 we will react accordingly, but currently there is no demand for a faster trace debug probe with more pins supported.

    The iMXRT 1050 is definitely on our radar. We even created a reference board with it that we should have in our lab soon: segger.com/products/debug-prob…050-trace-reference-board

    NXP claims 200 MHz on the trace GPIOs (which could again lead to overflows with complex applications), we will see how far we can push it ;)

    EDIT: Board is now released: segger.com/products/debug-prob…eference-boards/overview/

    Best regards,
    Nino
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