Hi,


I.MX 6 Ultra Light devices are currently not supported by the J-Link software.
Support will be implemented in a future release, but there is not a planned release date yet.

There is a bunch of MCIMX6?? devices. But I cant find mapping to Freescale devices naming. So which one should be used for IMX6UL.

On this site, there is an overview about iMX6 devices.: nxp.com/products/microcontroll…s:IMX6X_SERIES?cof=0&am=0

There is a Link to the overview of the "i.MX 6UltraLite Family of Applications Processors" series:
nxp.com/products/microcontroll…rm-cortex-a7-core:i.MX6UL

... where the data sheets can be found.
The naming scheme for UltraLight devices is MCIMX6Gxxx .

Best regards,
Niklas

Hello Niklas,

Well on our side we are able to make some good progress on debugging u-boot and barematel application on i.mx6ul-evk board using the segger j-link base.
we are able to place breakpoints, halt and resume in the source code of u-boot.
one limiting point for us at the moment is the following error when we reset the target, although the target gets reset but fails to halt.

Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.

As you have highlighted above that i.mx6ul devices are currently not supported, but is there any temporary patch/script to resolve the above mentioned error ? It will be highly appreciated and will allow us to proceed further.

Bit more detail of the above mentioned issue is as follows.

aarshad@aarshad-laptop:~/Work/Lennox/Lccd/Build_10052016/build_lccd$ /opt/SEGGER/JLink/JLinkExe
SEGGER J-Link Commander V5.12e (Compiled Apr 29 2016 15:06:32)
DLL version V5.12e, compiled Apr 29 2016 15:06:27

Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Mar 29 2016 18:45:53
Hardware version: V10.10
S/N: 50100439
License(s): GDB
VTref = 3.309V


Type "connect" to establish a target connection, '?' for help
J-Link>device cortex-a7
J-Link>connect
Please specify target interface:
J) JTAG (Default)
S) SWD
TIF>
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "CORTEX-A7" selected.


TotalIRLen = 13, IRPrint = 0x0101

**************************
WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

**************************

ARM AP[0]: 0x74770001, AHB-AP
ARM AP[1]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-001BB961 TMC
ROMTbl 0 [1]: 00002003, CID: B105900D, PID:04-004BB906 ECT / CTI
ROMTbl 0 [2]: 00003003, CID: B105900D, PID:04-004BB912 TPIU
ROMTbl 0 [3]: 00004003, CID: B105F00D, PID:04-001BB101
ROMTbl 0 [4]: 00020003, CID: B105100D, PID:04-000BB4A7 ROM Table
ROMTbl 1 [0]: 00010003, CID: B105900D, PID:04-005BBC07 Cortex-A7
Found Cortex-A7 r0p5
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
Data endian: little
Main ID register: 0x410FC075
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way
System control register:
Instruction endian: little
Level-1 instruction cache enabled
Level-1 data cache disabled
MMU disabled
Branch prediction enabled
Found 3 JTAG devices, Total IRLen = 13:
#0 Id: 0x5BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
#1 Id: 0x00000001
#2 Id: 0x0891D01D
Cortex-A7 identified.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Cortex-A/R (reset): Re-initializing debug logic.

**************************
WARNING: CPU not halted after Reset, halting using Halt request
**************************


****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.

J-Link>exit

Hi,

We are aware of this behavior. The iMX6UL requires some special handling to perform a proper reset. This is planned to be available in January 2017.

- Niklas