Hello uione,

a bit more information would be useful:
- Target hardware: Which CPU, Eval Board / Custom hardware?
- Which project is used: Sample project / Custom project?
- Which J-Link support is used: J-Link native support / J-Link RDI?
- J-Link hardware version?
- J-Link software version?

Best regards,
Alex

I have this same issue.

- Target hardware: Which CPU, Eval Board / Custom hardware? LPC2148/LPC2158, custom hardware

- Which project is used: Sample project / Custom project? Custom

- Which J-Link support is used: J-Link native support / J-Link RDI? Native

- J-Link hardware version? v 8.0

- J-Link software version? 4.12

What's going on? Can anyone offer an explanation?

Update.

Where this error occurs appears to be very random, which is quite frustrating. It may croak on a timer delay one time, then on a port pin assignment the next.

What's going on here?

I have the same RTCK problem with IAR C-SPY debugger.

I think this is probably a bug in IAR C-SPY debugger. Segger needs to cooperate with IAR to fix this problem ASAP.

Target hardware: ARM926EJ-S custom hardware with a lot of peripherals
Project used: a debug-only project
J-Link support used: J-Link native support
J-Link hardware version: V8.00
J-Link software version: V4.12

Hi all,

in general there are only a few situations in which an adaptive-clocking timeout occurs:

1. RTCK is not connected
2. If the CPU clock is switched off (temporarily).
For example this is the case on some devices when switching the CPU clock / using the PLL clock.
The CPU clock is switchd off, as long as the PLL clock is not stable.
The CPU clock is also switched off when executing a wait instruction
3. If the JTAG interface is disabled, temporarily. (For example if the bootloader of the device, which is executed after reset disables the JTAG interface during its execution)

Best regards
Alex