jtag chain initialization sequence

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  • jtag chain initialization sequence

    Hello,

    I've been working on a development board (hi-tech global v5ip7000) with a 1136jf-s core tile to develop a SOC prototype that includes my company's own IP core. So far we've done debugging on the ARM processor with the jlink probe, no problems at all, but when trying to insert our own TAP in the JTAG chain the probe is no longer able to detect the ARM processor, even though it correctly detects the change in IRLen (our TAP adds 4 bits of instruction register).
    Can anyone help by explaining the Jlink initialization sequence (IRlen detection, Device Identification register read sequence etc)? It would really help finding the problem if i knew exactly what was going on at the lowest level hardware interface.

  • Hello,

    the reason why the core is not recognized when you add an additional device is probably
    that it can not be recognized automatically.
    The recognition is currently based not only on the JTAG Id, but also on the IR Print and other information.

    Unfortunately, this does not work under all circumstances.
    What you will have to do is configure the scan chain:
    For J-Link commander, the command is
    Config <IRPre> <DRPre>

    Example:
    Config 0 0
    Config 4 1

    For details, please refer to the J-Link user manual.
    When writing your own program, you should use a similar command; check out the SDK Doc.

    --Rolf
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
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    Or you can contact us via e-mail.

  • Hi Rolf,

    Thanks for the advice.

    I've tried changing the chain configuration as you suggested but the outcome is the same. Perhaps i'm missing something. I'll go into more detail about the JTAG chain:

    TDI
    device 2: idcode = 0x07B36FOF (ARM 1136JF-S on coretile) IRLen = 5
    device 1: idcode = 0x2B900FOF (ARM ETM on coretile) IRLen = 4
    device 0: idcode = 0x56789AB1 (this is our TAP in FPGA) IRLen = 4
    TDO

    This chain configuration means there are 8 bits of IR and 2 devices between the ARM processor and TDO, so i tried config 8,2 which didn't work (of course i then tried every other plausible chain configuration).

    Anyway, I hooked up Chipscope to the design and monitored the TAP signals in the FPGA (device 0). The waveform shows me that the initial IR scan (the one mentioned in the user manual) goes well. Immediately afterwards jlink moves the TAP controller to SHIFT_DR and shifts out 3 bits then moves to PAUSE-DR at which point the chain should become inactive but instead i see changes on TDI (specifically, the jlink signature is being shifted in from the ETM and ARM core).
    This is very confusing and it may point to a signal integrity problem but i can't really tell without monitoring the JTAG signals provided by the jlink itself at the connector. Is there a way to monitor the jtag connector without using a logic analyzer? (i mean some sort of signal dump from jlink).

    Any help is much appreciated.

    Lucian