What's the electrical state of the SWD pins after flashing is complete ?

mirov · Nov 13th 2013, 6:26am

I'm using the JLink to flash very small and low power devices, and then often measuring the power consumption of them as they run the new code. The SWD pins are typically for convenience still connected to my target system, but I don't know if their electrical state (hi, low, Z) is assured. What is the expected state ? If "Z", what's the expected leakage current if the SWDCLK pin is pulled low and the SWDIO pin is pulled high (both with 100K resistors) ?
Also, is my understanding that the I/O drive levels are set by the voltage sensed on pin 1 of the 20 pin connector ? How low can this operate ?
Thanks, -Russ

SEGGER - Alex · Nov 19th 2013, 9:51pm

Hi Russ,

The SWD pins are typically for convenience still connected to my target system, but I don't know if their electrical state (hi, low, Z) is assured. What is the expected state ?

Depends on the environment.
If the debug session is still active, they are driven by J-Link.
If the debug session is finished and no(!) other software is connected to J-Link, the target interface is tri-stated.

Also, is my understanding that the I/O drive levels are set by the voltage sensed on pin 1 of the 20 pin connector ?

Yes.

How low can this operate ?

See J-Link spec... (segger.com/jlink_base.html)
1.2V

Best regards
Alex

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