Posts by davek

Hi Nino,

Atmel's EDBG with AS7 works fine.

I had also tried removing the isolation resistors so that there was no question that the EDBG didn't pose a conflict for the SWD J-link connection. No effect.

Thanks,

--Dave

Hi Nino,

There is no "project" at this time, I simply wanted to evaluate the part, so any of the testing done with J-link has been with an erased part (using AS7 and the ATMEL EDBG) OR with a simple blinking LED type test running.

I tried your test with Embedded Studio and obtained identical results (can't halt, can't erase, etc.) as with Jlink commander, and AS7.

As to identifying the demo board, there should be a sticker on the bottom with product code/revision and serial number on it. A09-2748 is the product code, then "/05" for revision 5.

Per Microchip DS70005321A, roughly page 45, it notes that the revision 4 of the PCB has early silicon mounted, revision 5 has rev "A0" mounted.

Pardon my repetition, but I want to make sure that you saw that Microchip support also can't get a J-Link to work with this demo board either.

Thanks,

--Dave

Hello Nino,

The second attachment to my original message is a J-Link Commander dialog showing that "halt" along with "rx 0" and "r" don't work. However, I once again repeated this process, from target power on, and have limited the test to just a "halt", and attached that output to this response.

The first attachment to my original message, the log file output, you referred to having the invalid memory access(s) is simply Atmel Studio 7 from the point of debugger attachment through attempted Chip Erase.

Referring to Microchip Document DS60001507A, the graphic on Page 48 shows AHB-APB Bridge B located at 0x41000000 and the DSU located at offset 0x2000. Referring to Section 12.9 at page 100, external DSU access must be offset by 0x0100, into memory mirrored from offset 0x0000. Therefore the 32 bit write to 0x41002100 attempts to set Chip Erase, the 8 bit read from 0x41002101 is a read of Status Register A, documented on pages 110 and 111 respectively.

The ATSAME54-XPRO board itself is Revision 5 and has a ATSAME54P20A mounted. I do not know if the "A" suffix is relevant, but do note that no distinction is made in the j-link dialog list of available devices.

Are you working with the same demo board and silicon revisions?

--Dave

Hi,

With a j-link connected to a Microchip ATSAME54-XPRO using a Segger 9 pin Cortex-M adapter, the j-link is unable to halt the CPU.

Using Atmel Studio 7.0 (Build 1645), programming and debugging this board is possible via Atmel's EDBG, and other ATSAM family parts work fine with the J-Link and AS7.

Microchip support duplicated this and suggested advising Segger of the issue.

I have tried Segger firmware/DLL versions from 6.16 through 6.22f, and I have tried removing the four isolation resistors that isolate the EDBG CPU.

I've attached two log files, one with AS7 establishing a connection and attempting a chip erase, and the other is a jlink.exe session log showing failed reset attempts.

Thanks,

-Dave