Posts by tj7

Yes.

Scenario:
- externally build elf file
- start debug it in ES
- externally rebuild elf file
- ES should show that elf file has changed

Is Embedded Studio has option to enable notification for user during debug session if externally build file has changed(recompiled) ?
Can it be feature request ?

I have enabled exitonerror option, but with verifybin it doesn't work. Why ?

Here is my script:

Quote

exitonerror 1
device STM32F405RG
if SWD
speed 400k
connect
r
h
loadfile ch.bin,0x8000000
w1 0x8000005,0x55
verifybin ch.bin,0x8000000
r
go
exit

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and logs:

Quote

Downloading file [ch.bin]...
Comparing flash [100%] Done.
Erasing flash [100%] Done.
Programming flash [100%] Done.
Verifying flash [100%] Done.
J-Link: Flash download: Bank 0 @ 0x08000000: 1 range affected (16384 bytes)
J-Link: Flash download: Total time needed: 1.030s (Prepare: 0.114s, Compare: 0.074s, Erase: 0.341s, Program: 0.473s, Verify: 0.001s, Restore: 0.024s)
O.K.

Writing 55 -> 08000005

Loading binary file ch.bin
Reading 81272 bytes data from target memory @ 0x08000000.
Verify failed @ address 0x08000005.
Expected 02 read 55
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Comparing flash [100%] Done.
Erasing flash [100%] Done.
Programming flash [100%] Done.
Verifying flash [100%] Done.
J-Link: Flash download: Bank 0 @ 0x08000000: 1 range affected (16384 bytes)
J-Link: Flash download: Total time needed: 1.272s (Prepare: 0.196s, Compare: 0.009s, Erase: 0.341s, Program: 0.610s, Verify: 0.001s, Restore: 0.112s)
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.

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Thank you. It is working correctly, I see all registers.

I'm using Embedded Studio v3.34a, I have externally build executable for Cortex-M project, target is STM32F411RC
Debugging is working correctly, but in View->Registers window I see only 5 registers group. [Blocked Image: https://thumb.ibb.co/ci3FEc/regs.png]
How to enable another registers ? GPIO, TIMx and others ?

Try Ctrl+J
Is it possible to remap it to another key ?

On PC I have IAR 8.20.
On RPi I have ARM GDB server with J-Link connected to STM32F405 via SWD.
RPi and STM32F405 are in high voltage enviroment, this setup is for safe debug.

I can't run IAR with remote J-link ARM GDB server on Raspberry Pi
I got message: Busy or Flash loader reported error. Here is logged all communications.
Is it configuration mistake ?

Hello

Number is: 260102579

Here is my screenshot.

Best Regards
tj

I have J-link EDU it worked with 6.12 and 6.16 firmware.
After update to 6.20c I got message: "The connected J-Link is defective" with jlink.exe standalone and with IAR debug. Debug breaks.
Two others my commercial J-Links BASE and PLUS works correctly with 6.20c

I have tested EDU with different SW and FW wersions, 6.12 SW works with correctly with 6.12 and 6.20FW, but 6.20SW display error with all FW versions.
How to fix it ?

What is the difference between BASE and Compact - is it only case ?
Or hardware differences like logic buffers, multiplexers, voltage levels ?

I will try, but it is hard to catch it, gpio with counter works correctly.
I often got "Failed to get CPU status" when run radio with RAIL library.

Hi Niklas

I will check on simple project.

Today I have another error in IAR.
Here is my screen: [Blocked Image: https://ibb.co/etcoKv] https://ibb.co/etcoKv

If this error occurs, choose:
- YES - I can't run the IAR debugger, despite many attempts, then I run jlink.exe connect to MCU without any problems, close jlink.exe, come back to IAR and debugger can start correctly.
- NO - debugger starts, but after 1-2s I got message "Failed to get CPU status after 4 retries Retry?"


I have checked on simple project, main with i++ counter, I don't have problems with stability.
I have stability issue and error "Failed to get CPU status after 4 retries Retry?" when my code are using other MCU peryferials: gpio, uart and radio.

Hi Niklas

No, I don't have low power mode.
It is better when chip is empty.
In external tool Simplicity Commander I click "Unlock debug access" or "Erase chip" - I don't have debugger breakdown.

I have unchecked this option, debugger starts without error every time, but has often problem with stability during debug, I got disconnect or retry window.
I come back this function, and put ticket do IAR support.

I have tested it today, in IAR debugger I often got error: Execution failure in flash loader
I have checked it in jlink console, works correctly.
Is there IAR or J-Link issue ?

Here are my logs:

"Thu Aug 03, 2017 13:53:38: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll)
Thu Aug 03, 2017 13:53:38: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
Thu Aug 03, 2017 13:53:38: Device "EFR32MG1PXXXF256" selected.
Thu Aug 03, 2017 13:53:38: JLINK command: ProjectFile = D:\Projekty\thread\sources\connector\settings\connector_EFR32MG1P-Debug.jlink, return = 0
Thu Aug 03, 2017 13:53:38: Device "EFR32MG1PXXXF256" selected.
Thu Aug 03, 2017 13:53:38: JTAG speed is initially set to: 32 kHz
Thu Aug 03, 2017 13:53:38: TotalIRLen = ?, IRPrint = 0x..FFFFFFFFFFFFFFFFFFFFFFF1
Thu Aug 03, 2017 13:53:38: Secured EFR32 device detected. This could cause problems during flash download.
Thu Aug 03, 2017 13:53:38: Note: Unsecuring will trigger a mass erase of the internal flash.
Thu Aug 03, 2017 13:53:38: Executing default behavior previously saved in the registry.
Thu Aug 03, 2017 13:53:38: Device will be unsecured now.
Thu Aug 03, 2017 13:53:38: Found SW-DP with ID 0x2BA01477
Thu Aug 03, 2017 13:53:38: Scanning APs, stopping at first AHB-AP found.
Thu Aug 03, 2017 13:53:38: AP[0] IDR: 0x24770011 (AHB-AP)
Thu Aug 03, 2017 13:53:38: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
Thu Aug 03, 2017 13:53:38: CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
Thu Aug 03, 2017 13:53:38: Found Cortex-M4 r0p1, Little endian.
Thu Aug 03, 2017 13:53:38: FPUnit: 6 code (BP) slots and 2 literal slots
Thu Aug 03, 2017 13:53:38: CoreSight components:
Thu Aug 03, 2017 13:53:38: ROMTbl[0] @ E00FF000
Thu Aug 03, 2017 13:53:38: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
Thu Aug 03, 2017 13:53:38: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
Thu Aug 03, 2017 13:53:38: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
Thu Aug 03, 2017 13:53:38: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
Thu Aug 03, 2017 13:53:38: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
Thu Aug 03, 2017 13:53:38: Setting AIRCR.SYSRESETREQ
Thu Aug 03, 2017 13:53:38: Hardware reset with strategy 0 was performed
Thu Aug 03, 2017 13:53:38: Initial reset was performed
Thu Aug 03, 2017 13:53:38: Found 1 JTAG device, Total IRLen = 4:
Thu Aug 03, 2017 13:53:38: Setting up GECKOP2 flash
Thu Aug 03, 2017 13:53:38: 1024 bytes downloaded and verified (16.13 Kbytes/sec)
Thu Aug 03, 2017 13:53:38: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.out
Thu Aug 03, 2017 13:53:38: Target reset
Thu Aug 03, 2017 13:53:38: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
Thu Aug 03, 2017 13:53:38: Execution failure in flash loader. Thu Aug 03, 2017 13:53:50: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll) "

"SEGGER J-Link Commander V6.16j (Compiled Jul 24 2017 18:42:58)
DLL version V6.16j, compiled Jul 24 2017 18:42:23

Connecting to J-Link via USB...O.K.
Firmware: Silicon Labs J-Link Pro OB compiled Mar 9 2017 14:47:50
Hardware version: V4.00
S/N: 440048406
IP-Addr: DHCP (no addr. received yet)
VTref = 3.329V

Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. : EFR32MG1PXXXF256
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
TIF>S
Specify target interface speed [kHz]. : 4000 kHz
Speed>
Device "EFR32MG1PXXXF256" selected.

Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Found SW-DP with ID 0x2BA01477
Scanning APs, stopping at first AHB-AP found.
AP[0] IDR: 0x24770011 (AHB-AP)
AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
Cortex-M4 identified.
J-Link>"

Here is my error log, appears in irregular intervals, tested with various speed, start from 35kHz.

"SEGGER J-Link Commander V6.16c (Compiled Jun 16 2017 18:15:26)
DLL version V6.16c, compiled Jun 16 2017 18:14:49

Connecting to J-Link via USB...O.K.
Firmware: Silicon Labs J-Link Pro OB compiled Mar 9 2017 14:47:50
Hardware version: V4.00
S/N: 440055730
IP-Addr: DHCP (no addr. received yet)
VTref = 3.323V

Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. : EFR32MG1BXXXF256
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
TIF>s
Specify target interface speed [kHz]. : 4000 kHz
Speed>
Device "EFR32MG1BXXXF256" selected.

Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
Found SW-DP with ID 0x2BA01477
Scanning APs, stopping at first AHB-AP found.
Found SW-DP with ID 0x2BA01477
Found SW-DP with ID 0x2BA01477
Scanning APs, stopping at first AHB-AP found.
AP[0] IDR: 0x24770011 (AHB-AP)
AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
CPUID reg: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite

****** Error: Connect: Communication error when trying to read IDR of AP[0].
J-Link>"

I got similar problem, is it J-link issue ?

"Wed Jun 21, 2017 12:41:08: IAR Embedded Workbench 8.11.2 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll)
Wed Jun 21, 2017 12:41:08: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\config\flashloader\SiliconLaboratories\FlashGECKOP2.mac
Wed Jun 21, 2017 12:41:08: Device "EFR32MG1BXXXF256" selected.
Wed Jun 21, 2017 12:41:08: JLINK command: ProjectFile = D:\Projects\client\settings\app_CSL002-Debug.jlink, return = 0
Wed Jun 21, 2017 12:41:08: Device "EFR32MG1BXXXF256" selected.
Wed Jun 21, 2017 12:41:08: Selecting SWD as current target interface.
Wed Jun 21, 2017 12:41:08: JTAG speed is initially set to: 100 kHz
Wed Jun 21, 2017 12:41:08: Found SW-DP with ID 0x2BA01477
Wed Jun 21, 2017 12:41:09: Found SW-DP with ID 0x2BA01477
Wed Jun 21, 2017 12:41:09: No AP preselected. Assuming that AP[0] is the AHB-AP
Wed Jun 21, 2017 12:41:09: AP-IDR: 0x24770011, Type: AHB-AP
Wed Jun 21, 2017 12:41:09: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
Wed Jun 21, 2017 12:41:09: Found Cortex-M4 r0p1, Little endian.
Wed Jun 21, 2017 12:41:09: FPUnit: 6 code (BP) slots and 2 literal slots
Wed Jun 21, 2017 12:41:09: CoreSight components:
Wed Jun 21, 2017 12:41:09: ROMTbl[0] @ E00FF000
Wed Jun 21, 2017 12:41:09: ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
Wed Jun 21, 2017 12:41:09: ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
Wed Jun 21, 2017 12:41:09: ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
Wed Jun 21, 2017 12:41:09: ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
Wed Jun 21, 2017 12:41:09: ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite
Wed Jun 21, 2017 12:41:09: Warning: Could not set S_RESET_ST
Wed Jun 21, 2017 12:41:09: Warning: CPU did not halt after reset.
Wed Jun 21, 2017 12:41:09: Warning: CPU could not be halted
Wed Jun 21, 2017 12:41:09: Core did not halt after reset, trying to disable WDT.
Wed Jun 21, 2017 12:41:10: Warning: CPU did not halt after reset.
Wed Jun 21, 2017 12:41:10: Warning: CPU could not be halted
Wed Jun 21, 2017 12:41:10: Warning: Could not set S_RESET_ST
Wed Jun 21, 2017 12:41:10: Found SW-DP with ID 0x2BA01477
Wed Jun 21, 2017 12:41:10: Using pre-configured AP[0] as AHB-AP to communicate with core
Wed Jun 21, 2017 12:41:10: Could not power-up system power domain.
Wed Jun 21, 2017 12:41:11: SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
Wed Jun 21, 2017 12:41:11: Found SW-DP with ID 0x2BA01477
Wed Jun 21, 2017 12:41:11: Using pre-configured AP[0] as AHB-AP to communicate with core
Wed Jun 21, 2017 12:41:11: AP-IDR: 0x24770011, Type: AHB-AP
Wed Jun 21, 2017 12:41:11: AHB-AP ROM: 0xE00FF000 (Base addr. of first ROM table)
Wed Jun 21, 2017 12:41:11: Found Cortex-M4 r0p1, Little endian.
Wed Jun 21, 2017 12:41:11: Warning: Failed to reset CPU. VECTRESET has confused core.
Wed Jun 21, 2017 12:41:11: Warning: CPU did not halt after reset.
Wed Jun 21, 2017 12:41:11: Warning: CPU could not be halted
Wed Jun 21, 2017 12:41:11: Core did not halt after reset, trying to disable WDT.
Wed Jun 21, 2017 12:41:11: Warning: CPU did not halt after reset.
Wed Jun 21, 2017 12:41:11: Warning: CPU could not be halted Wed Jun 21, 2017 12:41:12: Warning: Could not set S_RESET_ST "

Thank you for reply, all J-Link interfaces are working correctly now

Hello Nino,
Oce again:

I have two computers: A and B with the same hardware(i5 4460, Asus B85M-G) and software(Win7, IAR, Simplicity Studio, Segger J-Link).
I have J-Link Base and 6 Silicon Labs BRD4001A demo boards with build in J-link debug probe.

On computer B all 7x J-Links works correctly.
On computer A today I have only one working J-link debug probe.

On computer A fresh win7 installation all 7x J-Links worked correctly. At irregular intervals next J-Link had a problem with driver.
Today I have ony one working J-link interface on computer A.

6x J-links debug probe have problem with driver. In device manager in Another devices branch I see J-Link(for J-Link base - green led blinking) or J-link Pro OB(for Silabs BRD4001A) with exclamation mark.
I can not install driver, I have checked driver from Silabs and original from Segger site. I allways got message: Windows can't find driver for this device.

The only difference between computer A and B is the computer A I hibernate sometimes with attached J-link debug probe, perhaps this is a clue.

How to clean all J-Link drivers and others traces ?
Is it possible to debug this driver issue ?

Best regards

Tomasz