Hell Simon,
thank you for the information. I noticed that Ozone shows only AARCH32 CPU registers, even when the code is built for AARCH64 (and disassembly is correctly shown for this architecture). Is there a way to switch CPU registers display or AARCH64 register set is not supported? In the latter case, will it be supported?
Best regards,
Stefano
Hello,
I am interested in working with NXP's i.MX91 in a bare-metal setup. From your knowledge base, it looks like core initialization/reset/setup and flashing are not supported as of now. This is definitely an issue for bare-metal development on this CPU. Do you have plans to extend J-Link support for this CPU to include the missing features in the near future? If this is not the case, what other options can you suggest?
Thank you and best regards,
Stefano
Hello Simon,
thank you for the clarification. Here you find the page stating "J-Link debug probes offer full support for Espressif ESP32 devices" and "This update enables developers to debug and program Espressif's RISC-V-based microcontrollers".
Best regards,
Stefano
Hello,
the addition of support for ESP32 devices to J-Link was indeed great news - thank you.
While it is now possible to debug code from Ozone, ESP32 internal flash programming seems still not supported (although stated in the announcement, "debug and program").
Do you have plans to add support for flashing ESP32 via Ozone/J-Link?
Best regards
Stefano
Hello,
in our products, based on i.MXRT processors, we use alternate pinout for the QSPI flash used for boot. Although programming works generically fine, it looks like the Segger QSPI loader for these devices probes all the combination of pinouts for the primary FlexSPI controller in order to detect the correct pinout. This causes detection and/or operation problems if some pin of the primary port is used for any other function.
Is there a way to instruct the QSPI loader for i.MXRT to use a specific pinout for primary FlexSPI controller, skipping the detection phase? This is required for both J-Flash and J-Link.
Thank you in advance and best regards,
Stefano Voulaz
Hello,
I am working on a project based on i.MXRT1176, where both M4 and M7 cores are used. The problem is, I can see RTT output only from application running on M7 core.
Here follows some information about debug setup:
- Debugging is made via two Ozone sessions (M7 in download, M4 in attach)
- Each application uses its own RTT control block
- Address of control blocks is correctly detected by both Ozone instances (and buffer data is ktbg)
- RTT log from M7 is correctly displayed in M7 Ozone instance
- RTT log from M4 is not displayed in M4 Ozone instance, nor in RTT Viewer
- If M7 Ozone session is disconnected, then RTT log from M4 can be displayed in both Ozone and RTT Viewer
- J-link version 7.88e, Ozone version 3.30
What am I missing?
Best regards,
Stefano
Additional information
After disconnecting M7, if I re-attach to M7 core, then I can see RTT log from M4 in the terminal of the Ozone M7 session (although CB address is the one of M7 application).
If I disable and re-enable RTT in Ozone M4 session, the I see RTT log from M4 in both terminals.
