Microchip ATSAMs70n20
If I step in disassembly, it is fine. but when I step in the c source, it crashes at the switch/case statement.
key = getkey();
switch (key) // crash to hard fault if step this.
{
case RS_TRIG_CMD_PARTIAL:
Mon May 05, 2025 17:16:55: IAR Embedded Workbench 9.60.3 (C:\iar\ewarm-9.60.3\arm\bin\armPROC.dll)
Mon May 05, 2025 17:16:55: Loaded macro file: C:\iar\ewarm-9.60.3\arm/config/debugger/Microchip/SAMx70.dmac
Mon May 05, 2025 17:16:55: PC-locked license - IAR Embedded Workbench for ARM
Mon May 05, 2025 17:16:55: J-Link library version: 81001
Mon May 05, 2025 17:16:55: JLINK command: ProjectFile = D:\work\10420\firm_s10420_s70n20\settings\s10420_Debug.jlink, return = 0
Mon May 05, 2025 17:16:55: Device "ATSAMS70N20A" selected.
Mon May 05, 2025 17:16:55: DLL version: V8.10a, compiled Oct 2 2024 14:15:45
Mon May 05, 2025 17:16:55: Firmware: J-Link Pro V4 compiled Sep 22 2022 15:00:37
Mon May 05, 2025 17:16:55: Serial number: 174504252
Mon May 05, 2025 17:16:55: Selecting SWD as current target interface.
Mon May 05, 2025 17:16:55: JTAG speed is initially set to: 1000 kHz
Mon May 05, 2025 17:16:55: Found SW-DP with ID 0x0BD11477
Mon May 05, 2025 17:16:55: DPIDR: 0x0BD11477
Mon May 05, 2025 17:16:55: CoreSight SoC-400 or earlier
Mon May 05, 2025 17:16:55: Scanning AP map to find all available APs
Mon May 05, 2025 17:16:55: AP[1]: Stopped AP scan as end of AP map has been reached
Mon May 05, 2025 17:16:55: AP[0]: AHB-AP (IDR: 0x04770041, ADDR: 0x00000000)
Mon May 05, 2025 17:16:55: Iterating through AP map to find AHB-AP to use
Mon May 05, 2025 17:16:55: AP[0]: Core found
Mon May 05, 2025 17:16:55: AP[0]: AHB-AP ROM base: 0xE00FD000
Mon May 05, 2025 17:16:55: CPUID register: 0x410FC271. Implementer code: 0x41 (ARM)
Mon May 05, 2025 17:16:55: Cache: L1 I/D-cache present
Mon May 05, 2025 17:16:55: Found Cortex-M7 r0p1, Little endian.
Mon May 05, 2025 17:16:55: FPUnit: 8 code (BP) slots and 0 literal slots
Mon May 05, 2025 17:16:55: CoreSight components:
Mon May 05, 2025 17:16:55: ROMTbl[0] @ E00FD000
Mon May 05, 2025 17:16:55: [0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
Mon May 05, 2025 17:16:55: ROMTbl[1] @ E00FE000
Mon May 05, 2025 17:16:55: [1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
Mon May 05, 2025 17:16:55: ROMTbl[2] @ E00FF000
Mon May 05, 2025 17:16:55: [2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
Mon May 05, 2025 17:16:55: [2][1]: E0001000 CID B105E00D PID 000BB002 DWT
Mon May 05, 2025 17:16:55: [2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
Mon May 05, 2025 17:16:55: [2][3]: E0000000 CID B105E00D PID 000BB001 ITM
Mon May 05, 2025 17:16:55: [1][1]: E0041000 CID B105900D PID 000BB975 ETM-M7
Mon May 05, 2025 17:16:55: [0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
Mon May 05, 2025 17:16:55: I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
Mon May 05, 2025 17:16:55: D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
Mon May 05, 2025 17:16:55: Reset type: NORMAL (https://wiki.segger.com/J-Link_Reset_Strategies)
Mon May 05, 2025 17:16:55: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon May 05, 2025 17:16:55: Reset: Reset device via AIRCR.SYSRESETREQ.
Mon May 05, 2025 17:16:55: Hardware reset with strategy 0 was performed
Mon May 05, 2025 17:16:55: Initial reset was performed
Mon May 05, 2025 17:16:55: POWERTRACE: Emulator buffer size: 25768 bytes
Mon May 05, 2025 17:16:56: Loaded debugee: D:\work\10420\firm_s10420_s70n20\Debug\Exe\s10420.out
Mon May 05, 2025 17:16:59: Auto speed detection, JTAG speed is set to: 2000 kHz
Mon May 05, 2025 17:16:59: J-Link: Flash download: Bank 0 @ 0x00400000: 2 ranges affected (122880 bytes)
Mon May 05, 2025 17:16:59: J-Link: Flash download: Total: 2.841s (Prepare: 1.148s, Compare: 0.131s, Erase: 0.586s, Program & Verify: 0.931s, Restore: 0.043s)
Mon May 05, 2025 17:16:59: J-Link: Flash download: Program & Verify speed: 128 KB/s
Mon May 05, 2025 17:16:59: 175596 bytes downloaded and verified (59.56 Kbytes/sec)
Mon May 05, 2025 17:16:59: Download completed and verification successful.
Mon May 05, 2025 17:16:59: Reset type: NORMAL (https://wiki.segger.com/J-Link_Reset_Strategies)
Mon May 05, 2025 17:16:59: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Mon May 05, 2025 17:16:59: Reset: Reset device via AIRCR.SYSRESETREQ.
Mon May 05, 2025 17:16:59: Software reset was performed
Mon May 05, 2025 17:16:59: Target reset
Mon May 05, 2025 17:16:59: Memory map 'after startup completion point' is active
Mon May 05, 2025 17:18:04: Breakpoint hit: Code @ main.c:1025.14, type: default (auto)
Mon May 05, 2025 17:18:14: Breakpoint hit: Code @ main.c:1025.14, type: default (auto)
Mon May 05, 2025 17:19:07: Warning: Timeout while preparing target, RAMCode did not respond in time (PC = 0x0040D830, XPSR = 0x01000003, SP = 0x204005B0)!
Mon May 05, 2025 17:19:07: Failed to prepare RAMCode using RAM
Mon May 05, 2025 17:19:37: Breakpoint hit: Code @ main.c:1025.14, type: default (auto)
Mon May 05, 2025 17:21:07: Breakpoint hit: Code @ main.c:1025.14, type: default (auto)
Mon May 05, 2025 17:21:15: Breakpoint hit: Code @ main.c:1025.14, type: default (auto)
Mon May 05, 2025 17:21:25: Warning: Timeout while preparing target, RAMCode did not respond in time (PC = 0x0040D830, XPSR = 0x01000003, SP = 0x204005B0)!
Mon May 05, 2025 17:21:25: Failed to prepare RAMCode using RAM
Mon May 05, 2025 17:21:25: Breakpoint hit: Code @ main.c:582.2, type: default (auto)
Mon May 05, 2025 17:21:25: HardFault exception.
Mon May 05, 2025 17:21:25: The processor has escalated a configurable-priority exception to HardFault.
Mon May 05, 2025 17:21:25:
Mon May 05, 2025 17:21:25: An unaligned access error has occurred (CFSR.UNALIGNED).
Mon May 05, 2025 17:21:25:
Mon May 05, 2025 17:21:25: Exception occurred at PC = 0x0, LR = 0x0
Mon May 05, 2025 17:21:25:
Mon May 05, 2025 17:21:25: See the call stack for more information.
Mon May 05, 2025 17:21:25: The stack pointer for stack 'CSTACK' (currently 0x2040'05b0) is outside the stack range (0x2045'fc00 to 0x2045'ffff)