We have been using Segger J-Link plus for debug and programming purpose of one of our project development having RA6T1 Renesas MCU series. While testing JTAG SWD signal programming, we are capturing clock signals having rise and fall time in range of ~7ns. Whereas as per the JTAG SWD specification in Renesas RA6T1 MCU datasheet, the maximum rise and fall time limitation is 5ns:
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We are seeing this behavior with only one of the two segger J-link plus that we are using. With the other J-link plus the rise and fall time are in limit of 5ns.
Question is :
Is it normal to have this delta in rise and fall time? If yes, what is the acceptable range of rise and fall time for clock with J-link plus?
OR
It is erratic and some issue with the one J-link plus that we are using?