[SOLVED] Setting breakpoint without halting target

Hi,
Thank you for your inquiry.
Hardware breakpoints (HW BP) on embedded devices are very limited.
Thus, by default, the flash breakpoint (Flash BP) feature is enabled.
From your description I would assume that you have set more BPs than HW BPs are available,
so a Flash BP is set.

When setting a Flash BP, a flash download has to be executed and for this the target is halted.

To disable Flash BPs, please refer to:
- https://wiki.segger.com/J-Link_Command…DisableFlashBPs
- https://wiki.segger.com/J-Link_-_Web_control_panel#Settings

Could you please check if this resolves the delay?

BR
Fabian

Short info from my side:

For Cortex-M cores, HW breakpoints as well as SW breakpoints in RAM can be set without halting the CPU core.
The J-Link API supports this.

While Fabian is correct regarding SW breakpoints in flash require the CPU core to be halted, I doubt that SW breakpoints in flash are used here
because 35ms sounds very short for reprogramming a flash sector.

All of this sounds more like the DAVE IDE does simply not make use of the "can set while running" feature and explicitly halts the CPU core (unnecessarily) before setting a breakpoint.
We recommend to get in touch with Infineon regarding this.
SEGGER Ozone supports this feature and may be used in the meantime, until Infineon comes up with a fix for DAVE IDE: https://www.segger.com/products/devel…-link-debugger/