SEGGER - Alex Administrator

Just to make sure that we are on the same page: It was NOT a bug so there was no fix for it. It was an inconvenience (for very few customers) but a known design decision. If you have a headless system, you still won’t see any dialog boxes. However,…

I learned today that QSPI support was not added yet but I discussed with my colleague that he will work on it this week. If everything works flawlessly, it should be available in a beta version by the end of the week. BR Alex

Hi, While I understand your point, I hope that you understand ours as well: We can only list as supported what we can maintain in-house. This means we need to have permanent access to a HW that supports it. I will check with the RISC-V vendors we…

Hi, To the best of my knowledge, flash programming was supported together with generic debug support for the device. BR Alex

EDU Mini: SWD multi-drop will be supported in today's release (V6.96). Planned to be available in about 4-6 hours from now. BR Alex

You also need to distinguish C-level stepping and assembly single stepping. While a single step on assembler level have interrupts disabled, a C-level step (step over, step-into, ...) has interrupts enabled. For assembly step-over operations, interrupts…

@n1kt0: For the EDU Mini it is a bug that will be corrected. It is still under maintenance and shall support the RP2040. @misha: You misunderstood me. I never wrote that the V4 do not support multi-drop. But just because they do, does not mean that they…

Hi, Cortex-R5, in case your chip provides an AHB-AP, will work. If you are using a TI big endian Cortex-R5 device, additional steps need to be taken. BR Alex

Hello Mario, Can you provide a bitstream for an affordable FPGA board? (E.g. an ARTY board) So far, we did not have such a setup/implementation available on our desks, so it has not been implemented yet. The frustrating thing about the spec. is that…

Has a fair chance to work. However we do not guarantee it, as it has not been tested. BR Alex

Hi, (EDU Mini V1) => Need to check that internally. Not sure about multi-drop being supported. EDU / BASE / PLUS V11 ULTRA+ / PRO V5 J-Trace PRO Cortex / CortexM V2 Everything else is out of support and not guaranteed to work. BR Alex

Hi, the FW update is independent from the IDE / debug environment you are using. Before an FW update is released, it goes through an internal test that it updates to that version correctly and it is also verified that a forced downgrade is still…

Almost all NXP devices nowadays need special connect and reset sequences. For this, J-Link needs to know the exact device. You selected generic “Cortex-M33” which is most probably not sufficient here. Flash programming / erasing of course will also…

Thanks for the confirmation. Good to hear that you are up and running. We will consider these threads as closed. BR Alex

Hi, a new J-Link comes with support. We are currently in the process to define more precisely with how much support etc. BR Alex

You have the possibility to downgrade (see UM08001 which explains how to do it). However, in your case, it looks like something inhibits further FW replacement (no matter if a new or an old FW shall be flashed). So even your “recommendation for the…

Is it possible that WFI / WFE low power modes are used while using the motor? If you can provide a sample project that runs on an eval board, we can have a quick look. BR Alex

Hi, For a reliable instruction trace, you need (besides SWCLK and SWDIO) also TCLK and TDATA 0-3 (TDATA0 may be sufficient for slower core speeds). The trace pins are there for a reason... Theoretically, you can also output the ETM (instruction trace)…

You need an EDU / BASE / PLUS V10 or later. The V9 does not support SWD multi-drop. BR Alex

We still suspect that this issue is related to the disassembly issue you reported in this thread: [SOLVED] incorrect decoding of RISC-V instructions There is a new version (V6.94c) coming today which fixes the problem reported in the other thread.It…