Hoxford Beginner

  • Member since Jul 10th 2014
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  • Hoxford -

    Replied to the thread J-Link Debugging the R5 core on the Xilinx Ultrascale+ XCZU7EV7.

    Post
    After further evaluation, the memory access problems are due to the Ultrascale+ XCZU7EV7 DDR memory requiring a init procedure before it can be accessed. I'm working on creating a jlink init script using the Xilinx SDK's init process as a guide. Once I…
  • Hoxford -

    Posted the thread J-Link Debugging the R5 core on the Xilinx Ultrascale+ XCZU7EV7.

    Thread
    I am attempting to do a debug session on the arm R5_0 core of an Ultrascale+ XCZU7EV7 using a Jlink Plus and, so far, have had no luck getting it to work. My setup: - Xilinx ZCU104 Ulrascale+ evaluation board - SW6 is set to Jtag mode (on, on, on, on) -…