Hello, We have completed and tested the bit file for ArtyA7-35. If you require another build for another FPGA module please let us know. It includes basic functionality (abstract register/memory access) for a RV32I CPU. As part of our tests we have…
Hi Alex, As a quick update, we have finalized a build for an ARTY A7. We will proceed with our own tests next week and send you the bit file when done. Could you provide a method for sharing? Best, Mario.
Hi Alex, Can you please provide us with a sample constraints file for Arty with your preferred 5 JTAG pins so we can use it accordingly. Best, Mario