RISC-V debugging: Non standard values for DTMCS and DMI possible?

    • RISC-V debugging: Non standard values for DTMCS and DMI possible?

      I have a question regarding a chip with a non standard debugging interface.
      Is it possible to access a core with the segger debugger if the values for DTMCS and DMI have non standard values.


      Reason for this setup is the security core must not be added in the chain and the designer dont want to have a second TAP.

      So there are two DTMs behind one TAP:


      DAP Port --> ARM M33
      |
      --> TAP --> DTM(0x10/0x11) --> RISC-V
      |
      ---> DTM(0x12/0x13) --> RISC-V (security core)

      Is there any possibility to change the DTMCS and DMI IDs? Maybe in the in the JLinkScript?



      Thanks