[SOLVED] JLink support for RISC-V VexRiscv core

v01d · Jan 10th 2024, 12:54am

Would like to use JLink 'native' with this soft RISC-V core:
github.com/SpinalHDL/VexRiscv

Project uses OpenOCD + gdb, which means I cannot (as far as I know) use Segger's Ozone, a tool I find slim, right & fit (and fast) so to say (and not a fat ide..).

Is it possible ... ?

SEGGER - Alex · Jan 10th 2024, 9:17pm

As far as I understand, it should be possible.
Make sure this is part of your FPGA config:
github.com/SpinalHDL/VexRiscv#debugplugin

and afterwards, the core should be available via JTAG.
By using J-Link Commander, following this sequence:
wiki.segger.com/J-Link_cannot_…ty_using_J-Link_Commander
(use “RV32” as device name, JTAG as target interface and 1000 kHz as TIF speed)

You should be able to verify a successful connect.

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