[SOLVED] How to specify the romtab address for an AP when accessed by Jlink, such as in the jlinkscript

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  • [SOLVED] How to specify the romtab address for an AP when accessed by Jlink, such as in the jlinkscript

    Dear Segger Experts,

    Is it possible to specify the rom table address for an AP in the jlinkscript?

    I have a case that a Cortex-R52 core is connected with the Debug Apb Bus and accessed in AP[0](The structure can be seen in the attached picture).

    The rom table addess for the R52 is 0xE00A0000, but when using the Jlink to connect, it couldn't find the R52 tom table, just find the rom table addres (0x8000_0000)for debug apb.

    My test jlinkscript is as the following:
    ---------------------------------------------------------------------------
    void InitTarget(void) {
    int v;
    int Ctrl;
    Report("******************************************************");
    Report("J-Link script: R52. J-Link script");
    Report("******************************************************");
    CPU = 0x1404FFFF; // Pre-select that we have a Cortex-R52 (Wrong CPU type for CORTEX_R52 in the jlink script)

    JTAG_AllowTAPReset = 0; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection

    //
    // Power-up complete DAP
    //
    v = 0
    | (1 << 30) // System power-up
    | (1 << 28) // Debug popwer-up
    | (1 << 5) // Clear STICKYERR
    ;
    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, v);
    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (0 << 24) | (0 << 4)); // Select AP[0], bank 0
    Ctrl = 0
    | (2 << 0) // AP-access size. Fixed to 2: 32-bit
    | (1 << 4) // Auto increment TAR after read/write access.
    // After a successful Data Read/Write Register access, the address in the TAR is incremented by the size of the access.
    | (1 << 31) // Enable software access to the Debug APB bus.
    ;
    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);

    JTAG_SetDeviceId(0, 0x6BA00477); // 4-bits IRLen
    CORESIGHT_AddAP(0, CORESIGHT_APB_AP); // core R52
    CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
    CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); // core M7_0
    CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); // core M7_1
    CORESIGHT_IndexAPBAPToUse = 0; // Use AP[0] here to connect Cortex-R52
    }
    ------------------------------------------------------------------
    The jlink log is as the attached picture shows.
    You could see the rom table address for AP[0] scanned by jlink is 0x8000_0000， not the 0xE00A0000.

    So I wonder if there is a method to specify the rom table address to 0xE00A0000 in the jlink script when jlink scanning.

    Many thanks in advance!

    BR,
    Gavin
    Images

    • err.png

      83.24 kB, 865×622, viewed 411 times

    • debug_R52_structure.png

      24.46 kB, 526×529, viewed 296 times

    The post was edited 1 time, last by GavinLi5567 ().

  • Hi,

    The picture does not show the actual structure… The structure would be which AP is connected to what and which components are at what addresses.

    You can specify 3 things:
    1) The AP map
    2) Which AP to use
    3) Where to find the core debug registers

    If the R52 in your design is not discoverable through the DebugAP ROM table, you need to do (3) as well.
    Usually, the ROM table of the DebugAP has 1 entry that points to the ROM table of the R52 and this ROM table has an entry that specifies the address of the core debug registers.

    If you have a working script for another probe, we can most probably derive a J-Link script file from that
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Alex,

    Thanks for your reply.

    The following is the debug info from the manual I got:

    R52 Debug core0Xe00a0000Debug APB Interconnect
    Debug APB ROM table0x80000000*1
    0xE00FD000*2    		Debug APB Interconnect

    *1: For DAP direct access.
    *2: For Processor0 access (including DAP access via Processor0 debug interface).

    Table 37.4‑1 Connections between APs and DAPBUS interconnect

    DAPBUS interconnectDP / AP
    Slave interfaceSWJ-DP connecting JTAG/SWD
    Master interface 0APB-AP connecting to the Debug APB interconnect
    Master interface 1AHB-AP connecting to the Peripheral Bus
    Master interface 2AHB-AP connecting to the Processor0 debug interface
    Master interface 3AHB-AP connecting to the Processor1 debug interface
    Master interface 4AHB-AP connecting to the Debug Management Control



    Meanwhile, the digital engineer told me, the access way is: JTAG---DAP AP[0] ----- APB debug bus M15-----R52 rom table

    Table 37.4‑11 R52 debug resource memory map

    AddressAccess target
    0xe00a0000~0xe00affffR52 ROM table
    0xe00b0000~0xe00bffffCore Debug register
    0xe00c0000~0xe00cffffCore CTI register
    0xe00d0000~0xe00dffffCore PMU register
    0xe00e0000~0xe00effffCore Trace register



    Based on the above information, I've created a jlinkscript and now can connect R52 core, but I'm not sure if there's anything missing or that needs to be perfected.

    ========================= Jlinkscript ===================
    Please the attachement file - XC30x_Connect_Core2.jlinkscript.

    ======================= Jlink Log ========================

    ...
    ...
    Connecting to target via JTAG
    ConfigTargetSettings() start
    ConfigTargetSettings() end - Took 23us
    InitTarget() start
    ******************************************************
    J-Link script for C030_R52
    ******************************************************
    ===> Write 0x12345678 -> addr 0x30000000
    ===> Release Cortex_R52
    InitTarget() end - Took 5.12ms
    TotalIRLen = 4, IRPrint = 0x01
    JTAG chain detection found 1 devices:
    #0 Id: 0x00000000, IRLen: 04, Unknown device
    DPv0 detected
    AP map detection skipped. Manually configured AP map found.
    AP[0]: APB-AP (IDR: Not set)
    AP[1]: AHB-AP (IDR: Not set)
    AP[2]: AHB-AP (IDR: Not set)
    AP[3]: AHB-AP (IDR: Not set)
    AP[4]: AHB-AP (IDR: Not set)
    Using preconfigured AP[0] as APB-AP
    AP[0]: APB-AP found
    DebugRegs + CTI manually specified. ROM table scan skipped.
    Cortex-R52 @ 0xE00B0000 (configured)
    CoreCTI @ 0xE00C0000 (configured)
    Debug architecture: ARMv8.0
    8 code breakpoints, 8 data breakpoints
    Processor features:
    EL0 support: AArch32
    EL1 support: AArch32
    EL2 support: AArch32
    EL3 support: N/A
    FPU support: Single + Double + Conversion
    Current exception level: EL2
    Exception level AArch usage:
    EL0: AArch32
    EL1: AArch32
    EL2: AArch32
    EL3: AArch32
    Non-secure status: Non-secure
    Cache info:
    Inner cache boundary: none
    LoU Uniprocessor: 1
    LoC: 1
    LoU Inner Shareable: 1
    I-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way
    D-Cache L1: 16 KB, 64 Sets, 64 Bytes/Line, 4-Way
    Memory zones:
    Zone: "Default" Description: Default access mode
    Zone: "AP0" Description: MEM-AP (APB-AP)
    Zone: "AP1" Description: MEM-AP (AHB-AP)
    Zone: "AP2" Description: MEM-AP (AHB-AP)
    Zone: "AP3" Description: MEM-AP (AHB-AP)
    Zone: "AP4" Description: MEM-AP (AHB-AP)
    Cortex-R52 identified.
    J-Link>

    ======================== End ======================

    Thanks in advance!

    Gavin
    Files

    The post was edited 1 time, last by GavinLi5567 ().

  • Hi,


    GavinLi5567 wrote:

    Based on the above information, I've created a jlinkscript and now can connect R52 core, but I'm not sure if there's anything missing or that needs to be perfected.
    The script looks good.
    Well done!


    BR
    Alex
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.