[SOLVED] JLink takes several tries to connect to STM32H730

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  • [SOLVED] JLink takes several tries to connect to STM32H730

    Hello,
    with the most recent versions of JLink, the connection to the STM32H730 takes many tries.
    Typically I can connect in the JLink command line, but it takes two tries (the first "connect" will not work, while the second "connect" will work).
    If I re-launch JLink command line, the same behavior happens again (the first "connect" will never work).

    It was working with older JLink versions, so there must be a regression here.


    Source Code

    1. > jlink
    2. SEGGER J-Link Commander V7.92b (Compiled Aug 23 2023 4:01:42)
    3. DLL version V7.92b, compiled Aug 23 2023 14:00:04
    5. Connecting to J-Link via USB...O.K.
    6. Firmware: J-Trace PRO V2 Cortex-M compiled Jun 6 2023 10:51:16
    7. Hardware version: V2.00
    8. J-Link uptime (since boot): 8d 18h 29m 12s
    9. S/N: 752001898
    10. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    11. USB speed mode: Super speed (5 GBit/s)
    12. IP-Addr: DHCP (no addr. received yet)
    13. Emulator has RAWTRACE capability
    14. VTref=1.779V
    15. Type "connect" to establish a target connection, '?' for help
    17. J-Link>connect
    18. Please specify device / core. <Default>: STM32H730IB
    19. Type '?' for selection dialog
    20. Device>
    21. Please specify target interface:
    22. J) JTAG (Default)
    23. S) SWD
    24. T) cJTAG
    25. TIF>s
    26. Specify target interface speed [kHz]. <Default>: 4000 kHz
    27. Speed>
    28. Device "STM32H730IB" selected.
    30. Connecting to target via SWD
    31. ConfigTargetSettings() start
    32. ConfigTargetSettings() end - Took 12us
    33. InitTarget() start
    34. SWD selected. Executing JTAG -> SWD switching sequence.
    35. DAP initialized successfully.
    36. Can not attach to CPU. Trying connect under reset.
    38. SWD selected. Executing JTAG -> SWD switching sequence.
    39. DAP initialized successfully.
    40. Timeout while waiting for CPU to halt.
    41. Connecting to CPU via connect under reset failed.
    42. InitTarget() end - Took 662ms
    43. Connect failed. Resetting via Reset pin and trying again.
    45. ConfigTargetSettings() start
    46. ConfigTargetSettings() end - Took 8us
    47. InitTarget() start
    48. SWD selected. Executing JTAG -> SWD switching sequence.
    49. DAP initialized successfully.
    50. Can not attach to CPU. Trying connect under reset.
    51. SWD selected. Executing JTAG -> SWD switching sequence.
    52. DAP initialized successfully.
    53. Timeout while waiting for CPU to halt.
    54. Connecting to CPU via connect under reset failed.
    55. InitTarget() end - Took 661ms
    56. Cannot connect to target.
    59. J-Link>connect
    60. Device "STM32H730IB" selected.
    61. Connecting to target via SWD
    62. ConfigTargetSettings() start
    63. ConfigTargetSettings() end - Took 7us
    64. InitTarget() start
    65. SWD selected. Executing JTAG -> SWD switching sequence.
    66. DAP initialized successfully.
    67. Can not attach to CPU. Trying connect under reset.
    69. SWD selected. Executing JTAG -> SWD switching sequence.
    70. DAP initialized successfully.
    71. Timeout while waiting for CPU to halt.
    72. Connecting to CPU via connect under reset failed.
    74. InitTarget() end - Took 658ms
    75. ConfigTargetSettings() start
    76. ConfigTargetSettings() end - Took 7us
    77. InitTarget() start
    78. SWD selected. Executing JTAG -> SWD switching sequence.
    79. DAP initialized successfully.
    80. InitTarget() end - Took 6.47ms
    81. Found SW-DP with ID 0x6BA02477
    82. DPIDR: 0x6BA02477
    83. CoreSight SoC-400 or earlier
    84. Scanning AP map to find all available APs
    85. AP[3]: Stopped AP scan as end of AP map has been reached
    86. AP[0]: AHB-AP (IDR: 0x84770001)
    87. AP[1]: AHB-AP (IDR: 0x84770001)
    88. AP[2]: APB-AP (IDR: 0x54770002)
    89. Iterating through AP map to find AHB-AP to use
    90. AP[0]: Core found
    91. AP[0]: AHB-AP ROM base: 0xE00FE000
    92. CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
    93. Cache: L1 I/D-cache present
    94. Found Cortex-M7 r1p2, Little endian.
    95. FPUnit: 8 code (BP) slots and 0 literal slots
    96. CoreSight components:
    97. ROMTbl[0] @ E00FE000
    98. [0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
    99. ROMTbl[1] @ E00FF000
    100. [1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
    101. [1][1]: E0001000 CID B105E00D PID 000BB002 DWT
    102. [1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
    103. [1][3]: E0000000 CID B105E00D PID 000BB001 ITM
    104. [0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
    105. [0][2]: E0043000 CID B105900D PID 004BB906 CTI
    106. I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
    107. D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    108. Memory zones:
    109. Zone: "Default" Description: Default access mode
    110. Cortex-M7 identified.
    Display All

    Thanks,
    Florent

  • Can you post a screenshot of the old version that shows that multiple connects in a row work?

    I would be surprised if a popular chip like the STM32H5 series would be that broken in a generic way but nobody else ran into and reported it.

    Are you 100% sure that it was ONLY the J-Link version you changed and not also the target application that changed, which now maybe switches the debug pins to GPIO by accident or similar?
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Yes, it is working first time on JLink 7.68.
    It is the exact same board, with the same JTrace, and exactly the same connections (the only change is the JLink software).

    Source Code

    1. λ jlink
    2. SEGGER J-Link Commander V7.68 (Compiled Jul 14 2022 16:56:10)
    3. DLL version V7.68, compiled Jul 14 2022 16:54:28
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Trace PRO V2 Cortex-M compiled Jun 6 2023 10:51:16
    6. Hardware version: V2.00
    7. J-Link uptime (since boot): 0d 00h 27m 42s
    8. S/N: 752001898
    9. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    10. USB speed mode: Super speed (5 GBit/s)
    11. IP-Addr: DHCP (no addr. received yet)
    12. Emulator has RAWTRACE capability
    13. VTref=1.826V
    14. Type "connect" to establish a target connection, '?' for help
    15. J-Link>connect
    16. Please specify device / core. <Default>: EFR32BG22CXXXF352
    17. Type '?' for selection dialog
    18. Device>STM32H730IB
    19. Please specify target interface:
    20. J) JTAG (Default)
    21. S) SWD
    22. T) cJTAG
    23. TIF>s
    24. Specify target interface speed [kHz]. <Default>: 4000 kHz
    25. Speed>
    26. Device "STM32H730IB" selected.
    27. Connecting to target via SWD
    28. ConfigTargetSettings() start
    29. ConfigTargetSettings() end
    30. Found SW-DP with ID 0x6BA02477
    31. STM32 (connect): Can not attach to CPU. Trying connect under reset.
    32. Found SW-DP with ID 0x6BA02477
    33. Active write protected STM32 device detected.
    34. This could cause problems during flash download.
    35. Note: Unsecuring will trigger a mass erase of the internal flash.
    36. Executing default behavior previously saved in the registry.
    37. Device will be unsecured now.
    38. Found SW-DP with ID 0x6BA02477
    39. DPIDR: 0x6BA02477
    40. CoreSight SoC-400 or earlier
    41. Scanning AP map to find all available APs
    42. AP[3]: Stopped AP scan as end of AP map has been reached
    43. AP[0]: AHB-AP (IDR: 0x84770001)
    44. AP[1]: AHB-AP (IDR: 0x84770001)
    45. AP[2]: APB-AP (IDR: 0x54770002)
    46. Iterating through AP map to find AHB-AP to use
    47. AP[0]: Core found
    48. AP[0]: AHB-AP ROM base: 0xE00FE000
    49. CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
    50. Found Cortex-M7 r1p2, Little endian.
    51. FPUnit: 8 code (BP) slots and 0 literal slots
    52. CoreSight components:
    53. ROMTbl[0] @ E00FE000
    54. [0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
    55. ROMTbl[1] @ E00FF000
    56. [1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
    57. [1][1]: E0001000 CID B105E00D PID 000BB002 DWT
    58. [1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
    59. [1][3]: E0000000 CID B105E00D PID 000BB001 ITM
    60. [0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
    61. [0][2]: E0043000 CID B105900D PID 004BB906 CTI
    62. Cache: Separate I- and D-cache.
    63. I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
    64. D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    65. Cortex-M7 identified.
    66. J-Link>
    Display All
    However, I am using the JTrace Pro, which I suspect not many people are using, so it may be broken since quite a long time.

    Thanks,
    Florent

  • Hi Florent,
    I just gave this a quick try on the STM32H735G-DK (STM32H735).
    I could not test it on an STM32H730, as there are no evaluation boards available as far as I know,
    but both should behave the same from a debug standpoint.

    On our side it worked without any issues with J-Trace Pro V2 Cortex-M (see below).

    Do you have any target application running on your device?
    If so, does the same issue appear after erasing & power-cycling the device?

    Best regards,
    Fabian

    Source Code

    1. Firmware: J-Trace PRO V2 Cortex-M compiled Jun 6 2023 10:51:16
    2. Hardware version: V2.00
    3. J-Link uptime (since boot): 0d 00h 00m 01s
    4. S/N: 752060000
    5. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    6. USB speed mode: High speed (480 MBit/s)
    7. IP-Addr: DHCP (no addr. received yet)
    8. Emulator has RAWTRACE capability
    9. VTref=3.307V
    10. Device "STM32H730IB" selected.
    13. Connecting to target via SWD
    14. ConfigTargetSettings() start
    15. ConfigTargetSettings() end - Took 15us
    16. InitTarget() start
    17. SWD selected. Executing JTAG -> SWD switching sequence.
    18. DAP initialized successfully.
    19. InitTarget() end - Took 7.04ms
    20. Found SW-DP with ID 0x6BA02477
    21. DPIDR: 0x6BA02477
    22. CoreSight SoC-400 or earlier
    23. Scanning AP map to find all available APs
    24. AP[3]: Stopped AP scan as end of AP map has been reached
    25. AP[0]: AHB-AP (IDR: 0x84770001)
    26. AP[1]: AHB-AP (IDR: 0x84770001)
    27. AP[2]: APB-AP (IDR: 0x54770002)
    28. Iterating through AP map to find AHB-AP to use
    29. AP[0]: Core found
    30. AP[0]: AHB-AP ROM base: 0xE00FE000
    31. CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
    32. Cache: L1 I/D-cache present
    33. Found Cortex-M7 r1p2, Little endian.
    34. FPUnit: 8 code (BP) slots and 0 literal slots
    35. CoreSight components:
    36. ROMTbl[0] @ E00FE000
    37. [0][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
    38. ROMTbl[1] @ E00FF000
    39. [1][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
    40. [1][1]: E0001000 CID B105E00D PID 000BB002 DWT
    41. [1][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
    42. [1][3]: E0000000 CID B105E00D PID 000BB001 ITM
    43. [0][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
    44. [0][2]: E0043000 CID B105900D PID 004BB906 CTI
    45. I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
    46. D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    47. Memory zones:
    48. Zone: "Default" Description: Default access mode
    49. Cortex-M7 identified.
    Display All
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.