[SOLVED] PSoC6 (CY8C6XX7_CM0P_TM), cannot read SFLASH area with J-Link 7.68 and newer (7.66g and older work as expected)

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  • [SOLVED] PSoC6 (CY8C6XX7_CM0P_TM), cannot read SFLASH area with J-Link 7.68 and newer (7.66g and older work as expected)

    Hello,

    I have ran into issue with J-Link 7.68 (and newer, including 7.88e) and Infineon PSoC6. With newer J-Link versions, I'm not able to read SFLASH after successful connection to target.

    Logs from 7.66g, reading 0x16000600 in SFLASH area works:

    Source Code

    1. SEGGER J-Link Commander V7.66g (Compiled Jul 7 2022 10:37:30)
    2. DLL version V7.66g, compiled Jul 7 2022 10:35:46
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Link V11 compiled May 23 2023 14:44:38
    6. Hardware version: V11.00
    7. S/N: 851003787
    8. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    9. USB speed mode: High speed (480 MBit/s)
    10. VTref=1.819V
    13. Type "connect" to establish a target connection, '?' for help
    14. J-Link>power on
    15. J-Link>connect
    16. Please specify device / core. <Default>: CY8C6XX7_CM4
    17. Type '?' for selection dialog
    18. Device>CY8C6XX7_CM0P_TM
    19. Please specify target interface:
    20. J) JTAG (Default)
    21. S) SWD
    22. T) cJTAG
    23. TIF>s
    24. Specify target interface speed [kHz]. <Default>: 4000 kHz
    25. Speed>
    26. Device "CY8C6XX7_CM0P_TM" selected.
    29. Connecting to target via SWD
    30. ConfigTargetSettings() start
    31. *****************************************************************
    32. JLinkScript: Start 'ConfigTargetSettings' for Cortex-M0+ of CY8C6xx6/CY8C6xx7
    33. *****************************************************************
    34. ConfigTargetSettings() end
    35. InitTarget() start
    36. InitTarget() end
    37. Found SW-DP with ID 0x6BA02477
    38. DPIDR: 0x6BA02477
    39. CoreSight SoC-400 or earlier
    40. AP map detection skipped. Manually configured AP map found.
    41. AP[0]: MEM-AP (IDR: Not set)
    42. AP[1]: AHB-AP (IDR: Not set)
    43. AP[2]: AHB-AP (IDR: Not set)
    44. AP[1]: Core found
    45. AP[1]: AHB-AP ROM base: 0xF0000000
    46. CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
    47. Found Cortex-M0 r0p1, Little endian.
    48. FPUnit: 4 code (BP) slots and 0 literal slots
    49. CoreSight components:
    50. ROMTbl[0] @ F0000000
    51. [0][0]: E00FF000 CID B105100D PID 000BB4C0 ROM Table
    52. ROMTbl[1] @ E00FF000
    53. [1][0]: E000E000 CID B105E00D PID 000BB008 SCS
    54. [1][1]: E0001000 CID B105E00D PID 000BB00A DWT
    55. [1][2]: E0002000 CID B105E00D PID 000BB00B FPB
    56. [0][1]: F0002000 CID B105900D PID 000BB9A6 ???
    57. [0][2]: F0003000 CID B105900D PID 001BB932 MTB-M0+
    58. Cortex-M0 identified.
    59. J-Link>mem32 0x16000600 2
    60. 16000600 = 188AEA98 012F3824
    61. J-Link>
    Display All



    Logs from 7.68, reading 0x16000600 in SFLASH area fails:

    Source Code

    1. SEGGER J-Link Commander V7.68 (Compiled Jul 14 2022 16:49:29)
    2. DLL version V7.68, compiled Jul 14 2022 16:47:42
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Link V11 compiled May 23 2023 14:44:38
    6. Hardware version: V11.00
    7. J-Link uptime (since boot): 0d 00h 00m 17s
    8. S/N: 851003787
    9. License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    10. USB speed mode: High speed (480 MBit/s)
    11. VTref=1.822V
    14. Type "connect" to establish a target connection, '?' for help
    15. J-Link>connect
    16. Please specify device / core. <Default>: CY8C6XX7_CM0P_TM
    17. Type '?' for selection dialog
    18. Device>
    19. Please specify target interface:
    20. J) JTAG (Default)
    21. S) SWD
    22. T) cJTAG
    23. TIF>s
    24. Specify target interface speed [kHz]. <Default>: 4000 kHz
    25. Speed>
    26. Device "CY8C6XX7_CM0P_TM" selected.
    29. Connecting to target via SWD
    30. ConfigTargetSettings() start
    31. ConfigTargetSettings() end
    32. InitTarget() start
    33. InitTarget() end
    34. Found SW-DP with ID 0x6BA02477
    35. DPIDR: 0x6BA02477
    36. CoreSight SoC-400 or earlier
    37. AP map detection skipped. Manually configured AP map found.
    38. AP[0]: MEM-AP (IDR: Not set)
    39. AP[1]: AHB-AP (IDR: Not set)
    40. AP[2]: AHB-AP (IDR: Not set)
    41. AP[1]: Core found
    42. AP[1]: AHB-AP ROM base: 0xF0000000
    43. CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
    44. Found Cortex-M0 r0p1, Little endian.
    45. FPUnit: 4 code (BP) slots and 0 literal slots
    46. CoreSight components:
    47. ROMTbl[0] @ F0000000
    48. [0][0]: E00FF000 CID B105100D PID 000BB4C0 ROM Table
    49. ROMTbl[1] @ E00FF000
    50. [1][0]: E000E000 CID B105E00D PID 000BB008 SCS
    51. [1][1]: E0001000 CID B105E00D PID 000BB00A DWT
    52. [1][2]: E0002000 CID B105E00D PID 000BB00B FPB
    53. [0][1]: F0002000 CID B105900D PID 000BB9A6 ???
    54. [0][2]: F0003000 CID B105900D PID 001BB932 MTB-M0+
    55. SetupTarget() start
    56. ****************************************************
    57. ** Silicon: 0xE208, Family: 0x100, Rev.: 0x24 (B3)
    58. ** Flash Boot version: 1.20.1.45
    59. ** Chip Protection: NORMAL
    60. ****************************************************
    61. SetupTarget() end
    62. Cortex-M0 identified.
    63. J-Link>mem32 0x16000600 2
    64. Could not read memory.
    65. J-Link>
    Display All
    However reading 0x0800000 work on both versions as is expected:

    Source Code

    1. J-Link>mem32 0x16000600 2
    2. Could not read memory.
    3. J-Link>mem32 0x08000000 1
    4. 08000000 = 5C8422BD
    5. J-Link>


    Is there anyway to make reading SFLASH work with newer versions?

    -Jussi