I'm trying to use my jlink to debug Starfive JH7110, which has a 1+4 harts version of U74-MC. I could successfully connect to chip, but I don't know which hart is selected and how to choose specific hart. Anyone could help?
[ABANDONED] Risc-V core hart selection?
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I'm trying to set dmcontrol register to select hart, but commander always report using hart0. Is this a bug?
Script:
C Source Code
- int InitTarget(void)
- {
- //
- // TDI -> TAP_#1 -> TAP_#0 -> TDO
- //
- // TAP_#0 info:
- // Maybe E24?
- // IRLen: 5
- //
- // TAP_#1 info:
- // U74-MC here
- // IRLen: 5
- //
- //
- // Code to connect to TAP_#1
- //
- JLINK_JTAG_DRPre = 1;
- JLINK_JTAG_DRPost = 0;
- JLINK_JTAG_IRPre = 5;
- JLINK_JTAG_IRPost = 0;
- JLINK_JTAG_IRLen = 5;
- JLINK_SetDevice("U74-MC");
- return 0;
- }
- // Select needed hart
- // Seems Jlink could not handle multi-core debugging at the same time through script file?
- // Or there exists some APIs not written in official wiki that could handle this?
- int SetupTarget(void)
- {
- int ret;
- U32 dmcontrol_addr;
- U32 hasel_mask;
- U32 hartsello_mask;
- U32 hartselhi_mask;
- U32 dmcontrol_value;
- U32 hart_id;
- U32 hart_id_target;
- // Set wanted hart id here(0 is S7 core, 1~4 is U74 core)
- hart_id = 3;
- ret = 0;
- dmcontrol_addr = 0x10;
- hasel_mask = 0x04000000;
- hartsello_mask = 0x03FF0000;
- hartselhi_mask = 0x0000FFC0;
- // Core selection through writing DMI registers
- // First, do automatic configure
- // Needed or connection would fail
- ret = JLINK_RISCV_DMI_AutodetectDMISettings();
- if(ret < 0)
- {
- return ret;
- }
- // Second, read dmcontrol to get current hart;
- ret = JLINK_RISCV_DMI_ReadReg(dmcontrol_addr, &dmcontrol_value);
- if(ret < 0)
- {
- return ret;
- }
- hart_id_target = ((dmcontrol_value & hartsello_mask) >> 16) | ((dmcontrol_value & hartselhi_mask) << 4);
- JLINK_SYS_Report("********************************");
- JLINK_SYS_Report("Pre-selection info");
- JLINK_SYS_Report1("dmcontrol value is: ", dmcontrol_value);
- JLINK_SYS_Report1("Current hart id is: ", hart_id_target);
- JLINK_SYS_Report("********************************");
- // Third, modify dmcontrol value to select wanted hart.
- dmcontrol_value = dmcontrol_value | ((hart_id & (hartsello_mask >> 16)) << 16) | ((hart_id & (hartselhi_mask << 4)) >> 4);
- ret = JLINK_RISCV_DMI_WriteReg(dmcontrol_addr, dmcontrol_value);
- if(ret < 0)
- {
- return ret;
- }
- // Fourth, check if configure is successful
- ret = JLINK_RISCV_DMI_ReadReg(dmcontrol_addr, &dmcontrol_value);
- hart_id_target = ((dmcontrol_value & hartsello_mask) >> 16) | ((dmcontrol_value & hartselhi_mask) << 4);
- JLINK_SYS_Report("********************************");
- JLINK_SYS_Report("Post-selection info");
- JLINK_SYS_Report1("dmcontrol value is: ", dmcontrol_value);
- JLINK_SYS_Report1("Current hart id is: ", hart_id_target);
- JLINK_SYS_Report("********************************");
- return ret;
- }
And here's JLink Commander output:
Source Code
- SEGGER J-Link Commander V7.86h (Compiled Apr 12 2023 16:11:59)
- DLL version V7.86h, compiled Apr 12 2023 16:10:23
- Connecting to J-Link via USB...O.K.
- Firmware: J-Link V11 compiled Mar 28 2023 16:59:55
- Hardware version: V11.00
- J-Link uptime (since boot): 0d 00h 06m 32s
- S/N: 261011862
- License(s): FlashBP, GDB
- OEM: SEGGER-EDU
- USB speed mode: High speed (480 MBit/s)
- VTref=3.300V (fixed)
- Type "connect" to establish a target connection, '?' for help
- J-Link>connect
- Please specify device / core. <Default>: U74-MC
- Type '?' for selection dialog
- Device>
- Please specify target interface:
- J) JTAG (Default)
- S) SWD
- T) cJTAG
- TIF>
- Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
- JTAGConf>
- Specify target interface speed [kHz]. <Default>: 4000 kHz
- Speed>15000
- Device "U74-MC" selected.
- Connecting to target via JTAG
- ConfigTargetSettings() start
- ConfigTargetSettings() end - Took 6us
- InitTarget() start
- Device "U74-MC" selected.
- InitTarget() end - Took 1.15ms
- TotalIRLen = 10, IRPrint = 0x0021
- JTAG chain detection found 2 devices:
- #0 Id: 0x07110CFD, IRLen: 05, Unknown device
- #1 Id: 0x07110CFD, IRLen: 05, Unknown device
- Debug architecture:
- RISC-V debug: 0.13
- AddrBits: 7
- DataBits: 32
- IdleClks: 5
- Memory access:
- Via system bus: Yes (8/16/32/64-bit accesses are supported)
- Via ProgBuf: Yes (16 ProgBuf entries)
- Via abstract command (AAM): May be tried as last resort
- DataBuf: 2 entries
- autoexec[0] implemented: Yes
- Detected: RV64 core
- Temp. halting CPU for for feature detection...
- HW instruction/data BPs: 8
- Support set/clr BPs while running: No
- HW data BPs trigger before execution of inst
- CSR access via abs. commands: No
- Feature detection done. Restarting core...
- BG memory access support: Via SBA
- SetupTarget() start
- ********************************
- Pre-selection info
- dmcontrol value is: 0x00000001
- Current hart id is: 0x00000000
- ********************************
- ********************************
- Post-selection info
- dmcontrol value is: 0x00030001
- Current hart id is: 0x00000003
- ********************************
- SetupTarget() end - Took 3.56ms
- Memory zones:
- Zone: "Default" Description: Default access mode
- RISC-V identified.
- J-Link>halt
- pc = 000000004000AB9A sp = 0000000040060F00 ra = 000000004000ABA0
- gp = 0000000000000000 tp = 0000000040061000 fp = 0000000040060F30
- t0 = 0000000000000022 t1 = 0000000000000000 t2 = 0000000000000000
- t3 = 0000000000000000 t4 = 0000000000000000 t5 = 0000000000000000 t6 = 0000000000000000
- a0 = 0000000000000001 a1 = 0000000000000000 a2 = 0000000000000000 a3 = 0000000000090006
- a4 = 0000000002000000 a5 = 0000000000000808 a6 = 0000000000000000 a7 = 0000000000000000
- s1 = 0000000040061068 s2 = 0000000000000002 s3 = 0000000000000000 s4 = 0000000040042000
- s5 = 0000000040042020 s6 = 0000000000000000 s7 = 0000000000000018 s8 = 0000000000002000
- s9 = 000000004004EAB8 s10 = 0000000000000000 s11 = 0000000000000000
- J-Link>readcsr 0xF11
- CSR 0x0F11: 0x00000489
- J-Link>readcsr 0xF12
- CSR 0x0F12: 0x8000000000000007
- J-Link>readcsr 0xF13
- CSR 0x0F13: 0x04210427
- J-Link>readcsr 0xF14
- CSR 0x0F14: 0x00000000
- J-Link>readcsr 0x301
- CSR 0x0301: 0x8000000000901107
CSR 0x301(misa) also implies this is a S7 core(at hart 0) rather than a U74 core.