New Design RM48L952.
Using J-Link Ultra+ Version 4.4.
J Flash Version 7.20a
Initial Connection to the Board was successful. Good Log below:
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Loaded LED Flashing Program that was verified on same hardware Development Board. After initial Load, unable to load/connect or erase the chip. See Bad Log
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Is there any way to recover this chip? Any reason why this could have happened? Thanks for any help.
Chris
Using J-Link Ultra+ Version 4.4.
J Flash Version 7.20a
Initial Connection to the Board was successful. Good Log below:
Source Code
- Connecting ...
- - Connecting via USB to probe/ programmer device 0
- - Probe/ Programmer firmware: J-Link Ultra V4 compiled Sep 24 2021 16:41:09
- - Device "RM48L9X" selected.
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - TotalIRLen = 6, IRPrint = 0x01
- - JTAG chain detection found 1 devices:
- - #0 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - InitTarget() end
- - TotalIRLen = 10, IRPrint = 0x0011
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - DPv0 detected
- - AP map detection skipped. Manually configured AP map found.
- - AP[0]: AHB-AP (IDR: Not set)
- - AP[1]: APB-AP (IDR: Not set)
- - AP[2]: MEM-AP (IDR: Not set)
- - Using preconfigured AP[1] as APB-AP
- - AP[1]: APB-AP found
- - ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 007BBC14 Cortex-R4
- - Found Cortex-R4 r1p3
- - 6 code breakpoints, 2 data breakpoints
- - Debug architecture ARMv7.0
- - Data endian: little
- - Main ID register: 0x411FC143
- - TCM Type register: 0x00010001
- - MPU Type register: 0x00000C00
- - System control register:
- - Instruction endian: little
- - Level-1 instruction cache disabled
- - Level-1 data cache disabled
- - MPU disabled
- - Branch prediction enabled
- - SetupTarget() start
- - Executing SetupTarget()
- - Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Stop_mode
- - TMS570LS: HandleSetup(): Initializing ECC protected RAM
- - SetupTarget() end
- - Target interface speed: 1000 kHz (Auto)
- - VTarget = 3.248V
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - InitTarget() end
- - TotalIRLen = 10, IRPrint = 0x0011
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - DPv0 detected
- - AP map detection skipped. Manually configured AP map found.
- - AP[0]: AHB-AP (IDR: Not set)
- - AP[1]: APB-AP (IDR: Not set)
- - AP[2]: MEM-AP (IDR: Not set)
- - Using preconfigured AP[1] as APB-AP
- - AP[1]: APB-AP found
- - ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 007BBC14 Cortex-R4
- - Found Cortex-R4 r1p3
- - 6 code breakpoints, 2 data breakpoints
- - Debug architecture ARMv7.0
- - Data endian: little
- - Main ID register: 0x411FC143
- - TCM Type register: 0x00010001
- - MPU Type register: 0x00000C00
- - System control register:
- - Instruction endian: little
- - Level-1 instruction cache disabled
- - Level-1 data cache disabled
- - MPU disabled
- - Branch prediction enabled
- - SetupTarget() start
- - Executing SetupTarget()
- - TMS570LS: HandleSetup(): Initializing ECC protected RAM
- - SetupTarget() end
- - Executing init sequence ...
- - Initialized successfully
- - Target interface speed: 1000 kHz (Auto)
- - CPU clock frequency: 7466 kHz (Auto detected)
- - Found 2 JTAG devices. Core ID: 0x4BA00477 (None)
- - Connected successfully
Loaded LED Flashing Program that was verified on same hardware Development Board. After initial Load, unable to load/connect or erase the chip. See Bad Log
Source Code
- Connecting ...
- - Connecting via USB to probe/ programmer device 0
- - Probe/ Programmer firmware: J-Link Ultra V4 compiled Sep 24 2021 16:41:09
- - Device "RM48L9X" selected.
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - JTAG chain manually configured. JTAG chain auto-detection skipped
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, Unknown device
- - #1 Id: 0x4B8A002F, IRLen: 06, Unknown device
- - Can not find ICE-Pick (IDCODE mismatch). Expected 0x0000002F, found: 0xA0002108
- - InitTarget() end
- - JTAG chain manually configured. JTAG chain auto-detection skipped
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, Unknown device
- - Identified core does not match configuration. (Found: None, Configured: Cortex-R4)
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - InitTarget() end
- - JTAG chain manually configured. JTAG chain auto-detection skipped
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - ERROR: Could not power up debug port: Control/Status register reads 10000F02
- - Target interface speed: 1000 kHz (Auto)
- - VTarget = 3.284V
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - InitTarget() end
- - JTAG chain manually configured. JTAG chain auto-detection skipped
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - DPv0 detected
- - AP map detection skipped. Manually configured AP map found.
- - AP[0]: AHB-AP (IDR: Not set)
- - AP[1]: APB-AP (IDR: Not set)
- - AP[2]: MEM-AP (IDR: Not set)
- - Using preconfigured AP[1] as APB-AP
- - AP[1]: APB-AP found
- - Invalid ROM table component ID 0x02020202 @ 0x00000FF0 (expected 0xB105100D). Trying again at alternative offset.
- - Invalid ROM table component ID 0x02020202 @ 0x60000FF0 (expected 0xB105100D). Trying again at alternative offset.
- - ConfigTargetSettings() start
- - ConfigTargetSettings() end
- - InitTarget() start
- - Executing InitTarget()
- - TotalIRLen = 6, IRPrint = 0x01
- - J-Link script: ICEPick found, enabling Cortex-R4 core.
- - InitTarget() end
- - JTAG chain manually configured. JTAG chain auto-detection skipped
- - JTAG chain detection found 2 devices:
- - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
- - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
- - ERROR: Cortex-A/R (connect): Could not determine address of core debug registers. Incorrect CoreSight ROM table in device?
- - ERROR: Failed to connect.
- Could not establish a connection to target.
Chris