[ABANDONED] RM48 Not Connecting after initial Programming

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  • [ABANDONED] RM48 Not Connecting after initial Programming

    New Design RM48L952.
    Using J-Link Ultra+ Version 4.4.
    J Flash Version 7.20a

    Initial Connection to the Board was successful. Good Log below:

    Source Code

    1. Connecting ...
    2. - Connecting via USB to probe/ programmer device 0
    3. - Probe/ Programmer firmware: J-Link Ultra V4 compiled Sep 24 2021 16:41:09
    4. - Device "RM48L9X" selected.
    5. - ConfigTargetSettings() start
    6. - ConfigTargetSettings() end
    7. - InitTarget() start
    8. - Executing InitTarget()
    9. - TotalIRLen = 6, IRPrint = 0x01
    10. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    11. - TotalIRLen = 6, IRPrint = 0x01
    12. - JTAG chain detection found 1 devices:
    13. - #0 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    14. - InitTarget() end
    15. - TotalIRLen = 10, IRPrint = 0x0011
    16. - JTAG chain detection found 2 devices:
    17. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    18. - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    19. - DPv0 detected
    20. - AP map detection skipped. Manually configured AP map found.
    21. - AP[0]: AHB-AP (IDR: Not set)
    22. - AP[1]: APB-AP (IDR: Not set)
    23. - AP[2]: MEM-AP (IDR: Not set)
    24. - Using preconfigured AP[1] as APB-AP
    25. - AP[1]: APB-AP found
    26. - ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 007BBC14 Cortex-R4
    27. - Found Cortex-R4 r1p3
    28. - 6 code breakpoints, 2 data breakpoints
    29. - Debug architecture ARMv7.0
    30. - Data endian: little
    31. - Main ID register: 0x411FC143
    32. - TCM Type register: 0x00010001
    33. - MPU Type register: 0x00000C00
    34. - System control register:
    35. - Instruction endian: little
    36. - Level-1 instruction cache disabled
    37. - Level-1 data cache disabled
    38. - MPU disabled
    39. - Branch prediction enabled
    40. - SetupTarget() start
    41. - Executing SetupTarget()
    42. - Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Stop_mode
    43. - TMS570LS: HandleSetup(): Initializing ECC protected RAM
    44. - SetupTarget() end
    45. - Target interface speed: 1000 kHz (Auto)
    46. - VTarget = 3.248V
    47. - ConfigTargetSettings() start
    48. - ConfigTargetSettings() end
    49. - InitTarget() start
    50. - Executing InitTarget()
    51. - TotalIRLen = 6, IRPrint = 0x01
    52. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    53. - InitTarget() end
    54. - TotalIRLen = 10, IRPrint = 0x0011
    55. - JTAG chain detection found 2 devices:
    56. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    57. - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    58. - DPv0 detected
    59. - AP map detection skipped. Manually configured AP map found.
    60. - AP[0]: AHB-AP (IDR: Not set)
    61. - AP[1]: APB-AP (IDR: Not set)
    62. - AP[2]: MEM-AP (IDR: Not set)
    63. - Using preconfigured AP[1] as APB-AP
    64. - AP[1]: APB-AP found
    65. - ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 007BBC14 Cortex-R4
    66. - Found Cortex-R4 r1p3
    67. - 6 code breakpoints, 2 data breakpoints
    68. - Debug architecture ARMv7.0
    69. - Data endian: little
    70. - Main ID register: 0x411FC143
    71. - TCM Type register: 0x00010001
    72. - MPU Type register: 0x00000C00
    73. - System control register:
    74. - Instruction endian: little
    75. - Level-1 instruction cache disabled
    76. - Level-1 data cache disabled
    77. - MPU disabled
    78. - Branch prediction enabled
    79. - SetupTarget() start
    80. - Executing SetupTarget()
    81. - TMS570LS: HandleSetup(): Initializing ECC protected RAM
    82. - SetupTarget() end
    83. - Executing init sequence ...
    84. - Initialized successfully
    85. - Target interface speed: 1000 kHz (Auto)
    86. - CPU clock frequency: 7466 kHz (Auto detected)
    87. - Found 2 JTAG devices. Core ID: 0x4BA00477 (None)
    88. - Connected successfully
    Display All


    Loaded LED Flashing Program that was verified on same hardware Development Board. After initial Load, unable to load/connect or erase the chip. See Bad Log


    Source Code

    1. Connecting ...
    2. - Connecting via USB to probe/ programmer device 0
    3. - Probe/ Programmer firmware: J-Link Ultra V4 compiled Sep 24 2021 16:41:09
    4. - Device "RM48L9X" selected.
    5. - ConfigTargetSettings() start
    6. - ConfigTargetSettings() end
    7. - InitTarget() start
    8. - Executing InitTarget()
    9. - TotalIRLen = 6, IRPrint = 0x01
    10. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    11. - JTAG chain manually configured. JTAG chain auto-detection skipped
    12. - JTAG chain detection found 2 devices:
    13. - #0 Id: 0x4BA00477, IRLen: 04, Unknown device
    14. - #1 Id: 0x4B8A002F, IRLen: 06, Unknown device
    15. - Can not find ICE-Pick (IDCODE mismatch). Expected 0x0000002F, found: 0xA0002108
    16. - InitTarget() end
    17. - JTAG chain manually configured. JTAG chain auto-detection skipped
    18. - JTAG chain detection found 2 devices:
    19. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    20. - #1 Id: 0x4B8A002F, IRLen: 06, Unknown device
    21. - Identified core does not match configuration. (Found: None, Configured: Cortex-R4)
    22. - ConfigTargetSettings() start
    23. - ConfigTargetSettings() end
    24. - InitTarget() start
    25. - Executing InitTarget()
    26. - TotalIRLen = 6, IRPrint = 0x01
    27. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    28. - InitTarget() end
    29. - JTAG chain manually configured. JTAG chain auto-detection skipped
    30. - JTAG chain detection found 2 devices:
    31. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    32. - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    33. - ERROR: Could not power up debug port: Control/Status register reads 10000F02
    34. - Target interface speed: 1000 kHz (Auto)
    35. - VTarget = 3.284V
    36. - ConfigTargetSettings() start
    37. - ConfigTargetSettings() end
    38. - InitTarget() start
    39. - Executing InitTarget()
    40. - TotalIRLen = 6, IRPrint = 0x01
    41. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    42. - InitTarget() end
    43. - JTAG chain manually configured. JTAG chain auto-detection skipped
    44. - JTAG chain detection found 2 devices:
    45. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    46. - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    47. - DPv0 detected
    48. - AP map detection skipped. Manually configured AP map found.
    49. - AP[0]: AHB-AP (IDR: Not set)
    50. - AP[1]: APB-AP (IDR: Not set)
    51. - AP[2]: MEM-AP (IDR: Not set)
    52. - Using preconfigured AP[1] as APB-AP
    53. - AP[1]: APB-AP found
    54. - Invalid ROM table component ID 0x02020202 @ 0x00000FF0 (expected 0xB105100D). Trying again at alternative offset.
    55. - Invalid ROM table component ID 0x02020202 @ 0x60000FF0 (expected 0xB105100D). Trying again at alternative offset.
    56. - ConfigTargetSettings() start
    57. - ConfigTargetSettings() end
    58. - InitTarget() start
    59. - Executing InitTarget()
    60. - TotalIRLen = 6, IRPrint = 0x01
    61. - J-Link script: ICEPick found, enabling Cortex-R4 core.
    62. - InitTarget() end
    63. - JTAG chain manually configured. JTAG chain auto-detection skipped
    64. - JTAG chain detection found 2 devices:
    65. - #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    66. - #1 Id: 0x4B8A002F, IRLen: 06, TI ICEPick
    67. - ERROR: Cortex-A/R (connect): Could not determine address of core debug registers. Incorrect CoreSight ROM table in device?
    68. - ERROR: Failed to connect.
    69. Could not establish a connection to target.
    Display All
    Is there any way to recover this chip? Any reason why this could have happened? Thanks for any help.


    Chris