[SOLVED] support for Cortex-A35 processor

einrock · Nov 9th 2022, 1:52am

I am designing the cortex-a35 based SoC and I have the jlink plus model (version 11).
so, I am wondering if it is supported to connect cortex-a35 processor with jlink plus or other jlink models.

we designed cortex-a35 based FPGA now.
but, the connection to the FPGA was not successful yet with following message output.

(please refer to the attached file)

SEGGER - Alex · Nov 15th 2022, 11:31pm

You have a CoreSight SoC-600 setup, so the following is done by J-Link:
J-Link expects a ROM table located at the address indicated by DP.BASEPTR0.
This top-level ROM table is the scanned for the existence of an APB-AP.
The APB-AP itself provides a ROMBASE register that indicates the start of the ROM table in the AP address space. That ROM table is then scanned for the core base address and core CTI base address.

If you have a faulty FPGA image with no ROM tables or wrong addresses being indicated by the registers, you need to manually setup the location of the APB-AP, core and core CTI,
via J-Link script files.

wiki.segger.com/J-Link_script_files

wiki.segger.com/images/5/54/Ex…s_NXP_S32V234.JLinkScript

einrock · Nov 16th 2022, 1:46pm

Thanks a lot, Alex
I'll check what you said.
I think the site you pointed out will be helpful.

SEGGER - Alex · Nov 17th 2022, 10:19pm

Closed this for now. If re-open is required, please PM.

[SOLVED] support for Cortex-A35 processor

[SOLVED] support for Cortex-A35 processor

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